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參數(shù)資料
| 型號(hào)： | LC8901 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Digital Audio Interface Receiver |
| 中文描述： | 數(shù)字音頻接口接收器 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 177K |
| 代理商： | LC8901 |
Microprocessor Interface Output
The table lists the content of the bits D0 to D15 in the microprocessor interface format.
Interpretation of Bits D1 and D2
1. The #1 state is the state in which the data was cleared by a PLL lock error.
2. The initial settings of the modes immediately after the XMODE pin is switched from low to high are all low level.
However, D1 and D2 will indicate the #1 state.
3. The microprocessor data output registers are all cleared to 0 when PLL locking is lost. However, D1 and D2 will
indicate the #1 state.
4. The interval between two microprocessor data readout operations must be at least 6 ms. Also, when PLL locking is
lost the microprocessor must wait at least 6 ms after the error signal goes low before accessing data.
FS Code
The SUB1 and SUB2 pins indicate the input data sampling frequency.
The #1 state is the state in which the data was cleared by a PLL lock error.
Lock and Errors
1. LOCK pin: This pin goes high when preamble detection has succeeded for 2 consecutive frames and thus indicates
the PLL locked state. This pin is low at all other times. In particular, it is low when the XMODE pin is low, when the
STOP pin is high, and in analog source mode.
2. ERROR pin: Goes high when an error exists in the input data or when the PLL circuit is in the unlocked state. When
the data returns to normal it holds the high level for about 200 to 300 ms and then falls to low. This period is
inversely proportional to the input data sampling frequency. This pin is high when the XMODE pin is low, when the
STOP pin is high, and in analog source mode.
3. Data processing when errors occur: The table below lists the data processing that is performed when an error occurs.
Note: The term “C bit data” means data that was decoded from the channel status bit.
When there is no data input to the data demodulation system, the system automatically switches from PLL
operation to the crystal oscillator and enters analog source mode.
These pins indicate a state identical to a PLL lock error in any of the following cases: The STOP pin is high, the
XMODE pin is low, or the system is in analog source mode.
No. 4079-11/15
LC8901, 8901Q
Bit
Meaning
D0
Invalid bit. A low level is always output.
D1
D2
Indicate the sampling frequency.
Correspond to the 2 external output port pins.
D3
Indicates the copy flag.
Low: copy protected, high: copying allowed.
D4
Outputs the first bit in the channel status bits.
D5 to D12
These bits serially output the 8 bits of the channel status category code.
D13 D15
Invalid bit. A low level is always output.
Sampling frequency
32 kHz
44.1 kHz
48 kHz
#1
D1
H
L
L
H
D2
H
L
H
L
Sampling frequency
32 kHz
44.1 kHz
48 kHz
#1
SUB1
H
L
L
H
SUB2
H
L
H
L
Error type
Audio output data
C bit output data
Continuous parity errors for up to 8 cycles
The previous data value is output
Continuous parity errors for 9 or more cycles
All zero data is output
Held
PLL lock error
All zero data is output
Data is cleared and the #1 state is indicated.
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| LC8903 | Digital Audio Interface Receiver(數(shù)字音頻接口接收器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC8901Q | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8902 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8902Q | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8903 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Digital Audio Interface Receiver |
| LC8903/8903Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Audio Interface Receiver |
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