參數(shù)資料
型號(hào)： LC87F72C8A
廠商： Sanyo Electric Co.,Ltd.
英文描述： 8-Bit Single Chip Microcontroller with 128 KB Flash Memory and 2048-Byte RAM On Chip
中文描述： 8位單片機(jī)微控制器128 kB的閃存和2048字節(jié)的片上內(nèi)存
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 717K
代理商： LC87F72C8A
LC87F72C8A
No.6712-10/24
Port Configuration
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Terminal
Option applies to: Options
Note 1Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00-03, P04-07).
* Note 1: Connect as follows to reduce noise on VDD.
VSS1, VSS2 and VSS3 must be connected together and grounded.
*Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for ports. When the
VDD2 is not backed up, the port level does not become “H” even if the port latch is in the “H” level. Therefore,
when the VDD2 is not backed up and the port latch is “H” level, the port level is unstable in the HOLD mode, and
the back up time becomes shorter because the through current runs from VDD to GND in the input buffer.
If VDD2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit in the HOLD
mode so that the port level becomes “L” level and unnecessary current consumption is prevented.
Output Form
Pull-up resistor
1
CMOS
Programmable
(Note 1)
None
P00 to P07
each bit
2
Nch-open drain
1
CMOS
Programmable
P10 to P17
each bit
2
Nch-open drain
Programmable
1
CMOS
Programmable
P30 to P35
each bit
2
Nch-open drain
None
P70
–
None
Nch-open drain
Programmable
P71 to P73
–
None
CMOS
Programmable
P80 to P87
–
None
Nch-open drain
None
S0/PA0 to
S47/PF7
–
None
CMOS
Programmable
COM0/PL0 to
COM3/PL3
V1/PL4 to
V3/PL6
XT1
–
None
Input only
None
–
None
Input only
None
–
None
Input only
None
XT2
–
None
Output for 32.768kHz crystal
oscillation
None
LSI
VDD1
Back-up capacitors *2 VDD2
VDD3
VSS2
VSS1
Power
VSS3
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