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參數(shù)資料
| 型號： | LC87F65C8A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8-Bit Single Chip Microcontroller with 128KB(131072 ×8 bits) ROM and 2048 Byte(2048 ×8 bits) RAM On Chip(8位單片微控制器（帶片上128K（131072 ×8 bit）字節(jié)ROM和2048(2048 ×8 bits)字節(jié)RAM）) |
| 中文描述： | 8位單片機微控制器的128KB（131072 × 8位）光盤和2048字節(jié)（2048 × 8位）片上的RAM（8位單片微控制器（帶片上128K的（131072 × 8位）光盤和2048字節(jié)（2048 × 8位）字節(jié)的RAM）） |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 684K |
| 代理商： | LC87F65C8A |
LC87F65C8A
15/24
4. Serial Input/Output Characteristics at Ta=-20
°
C to +70
°
C, VSS1=VSS2=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5–5.5
min.
4/3
max.
unit
Cycle Time
Low Level
pulse width
tSCK(1)
tSCKL(1)
tSCKLA(1)
tSCKH(1)
tSCKHA(1)
tSCK(2)
tSCKL(2)
tSCKH(2)
tSCK(3)
tSCKL(3)
tSCKLA(2)
tSCKH(3)
tSCKHA(2)
tSCK(4)
tSCKL(4)
tSCKH(4)
t
sDI
2/3
2/3
2/3
High Level
pulse width
SCK0(P12) Refer to figure 6
3
Cycle Time
Low Level
pulse width
High Level
pulse width
Cycle Time
Low Level
pulse width
2
1
1
I
SCK1(P15) Refer to figure 6
4.5–5.5
4/3
t
CYC
1/2
3/4
1/2
High Level
pulse width
SCK0(P12) CMOS output option
Refer to figure 6
4.5–5.5
2
tSCK
Cycle Time
Low Level
pulse width
High Level
pulse width
2
tCYC
1/2
S
O
SCK1(P15) CMOS output option
Refer to figure 6
4.5–5.5
1/2
tSCK
Data set-up time
0.03
S
Data hold time
t
hDI
SI0(P10),
SI1(P13),
SB0(P11),
SB1(P14)
Measured with respect
to SI0CLK leading
edge.
Refer to figure 6
4.5–5.5
0.03
S
Output delay time
tdDO
SO0(P12),
SO1(P15),
SB0(011),
SB1(P14)
When port is open
drain: Time delay from
SI0CLK trailing edge
to the SO data change.
Use pull-up resistor
(1k
) when open drain
output selected.
Refer to figure 6
4.5–5.5
1/3
tCYC
+0.05
μ
s
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