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參數(shù)資料
| 型號： | LC877424A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8 Bit Single Chip Microcontroller Incorporating 48K/40K/32K/24K Byte ROM and 1536 byte RAM on Chip |
| 中文描述： | 8位單片機微控制器納入48K/40K/32K/24K字節(jié)ROM和1536字節(jié)的片上內(nèi)存 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 342K |
| 代理商： | LC877424A |
LC877448A/40A/32A/24A
No.7776-3/22
Continued from preceding page.
Base Timer
1) The clock signal can be selected from any of the following:
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts of five different time intervals are possible.
(9) High-speed clock counter
Countable up to 20MHz clock (when using 10MHz main clock)
Real time output
(10) Serial-interface
SIO 0: 8 bit synchronous serial interface
1) LSB first / MSB first is selectable
2) Internal 8 bit baud-rate generator (fastest clock period 4 / 3 tCYC)
3) Consecutive automatic data communication (1 to 256 bits)
SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2 to 512 tCYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8 to 2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2 to 512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
(11) AD converter
8 bits × 15 channels
(12) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal)
Noise rejection function (noise rejection filter’s time constant can be selected from 1 / 32 / 128 tCYC)
(13) Watchdog timer
The watching time period is determined by an external RC.
Watchdog timer can produce interrupt or system reset
(14) Interrupts: 20 sources, 10 vectors
1) Three priority (low, high and highest) multiple interrupts are supported.
During interrupt handling, an equal or lower priority interrupt request is postponed.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
Vector
Selectable level
Interrupt signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2 / T0L / INT4
4
0001BH
H or L
INT3 / Base timer / INT5
5
00023H
H or L
T0H
6
0002BH
H or L
T1L / T1H
7
00033H
H or L
SIO0
8
0003BH
H or L
SIO1
9
00043H
H or L
ADC / MIC / T6 / T7
10
0004BH
H or L
Port 0 / T4 / T5
Priority Level: X > H > L
For equal priority levels, vector with lowest address takes precedence.
(15) Subroutine stack levels: 768 levels max. Stack is located in RAM.
(16) Multiplication and division
16 bit × 8 bit (executed in 5 cycles)
24 bit × 16 bit (12 cycles)
16 bit ÷ 8 bit (8 cycles)
24 bit ÷ 16 bit (12 cycles)
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| LC877432A | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:8 Bit Single Chip Microcontroller Incorporating 48K/40K/32K/24K Byte ROM and 1536 byte RAM on Chip |
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| LC877448A | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:8 Bit Single Chip Microcontroller Incorporating 48K/40K/32K/24K Byte ROM and 1536 byte RAM on Chip |
| LC877648B | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:8-bit 1-chip Microcontroller |
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