參數(shù)資料
型號(hào)： LC86P7248
廠商： Sanyo Electric Co.,Ltd.
英文描述： 8-Bit Single-Chip Microcontroller with the One-Time Programmable PROM Built in
中文描述： 8位單片機(jī)與一次性可編程PROM的內(nèi)置
文件頁(yè)數(shù)： 12/20頁(yè)
文件大?。?/td> 651K
代理商： LC86P7248
LC86P7248
No.6838-12/20
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5 to 6.0
min.
0
max.
±
0.2
unit
VODLS
S0 to S47
Deference voltage
to ideal value
VLCD, 2/3VLCD,
1/3VLCD
LCD output
regulation
VODLC
COM0 to COM3
Deference voltage
to ideal value
VLCD, 2/3VLCD,
1/2VLCD, 1/3VLCD
4.5 to 6.0
0
±
0.2
V
RLCD(1)
Resistance at a
ladder resistor
Resistance at a
ladder resistor
1/2R mode
4.5 to 6.0
60
LCD ladder
resistor
RLCD(2)
4.5 to 6.0
30
Pull-up MOS
Tr. resistor
Rpu
Ports 0, 1, 3
Ports A,B,C,D,E,F
Ports 70, 71, 72, 73
VOH=0.9VDD
4.5 to 6.0
15
40
70
k
Hysteresis
voltage
VHIS
Port 1
Ports 70, 71, 72, 73
RES
All pins
Output disable
4.5 to 6.0
0.1VDD
V
Pin
capacitance
CP
f=1MHz
Unmeasurement
terminals for the
input are set to
VSS level.
Ta=25
°
C
4.5 to 6.0
10
pF
4. Serial Input/Output Characteristics at Ta=-30
°
C to +70
°
C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5 to 6.0
min.
2
1
max.
unit
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set up time
Data hold time
Output delay time
(Serial clock is
external clock)
t
CKCY
(1)
t
CKL
(1)
I
t
CKH
(1)
SCK0,
SCK1
Refer to figure 5.
1
t
CKCY
(2)
t
CKL
(2)
2
1/2
t
CKCY
1/2
t
CKCY
S
O
t
CKH
(2)
SCK0,
SCK1
Use pull-up
resistor (1k
)
when open drain
output.
Refer to figure 5.
Data set-up to
SCK0, 1
Data hold from
SCK0, 1
Refer to figure 5.
4.5 to 6.0
t
CYC
t
ICK
4.5 to 6.0
0.1
S
t
CKI
SI0,SI1
SB0,SB1
4.5 to 6.0
0.1
t
CKO(1)
4.5 to 6.0
7/12tCYC
+0.2
S
Output delay time
(Serial clock is
internal clock)
t
CKO(2)
SO0, SO1
SB0, SB1
Use pull-up
resistor (1k
)
when open drain
output.
Data hold from
SCK0, 1
Refer to figure 5.
4.5 to 6.0
1/3tCYC
+0.2
μ
s
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