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參數(shù)資料
| 型號： | LC86F8208A* |
| 文件頁數(shù)： | 12/21頁 |
| 文件大?。?/td> | 670K |
LC86F1216A
No.6686-12/21
4. Serial Input/Output Characteristics at Ta=0
°
C to +50
°
C, VSS=0V
Ratings
Parameter
Symbol
Pins
Conditions
VDD[V]
3.15-3.85
3.15-3.85
Min.
2
1
Typ.
Max.
Unit
Cycle
Low level
pulse width
High level
pulse width
Cycle
Low level
pulse width
High level
pulse width
Data set-up time
Data hold time
Output delay
time
(Using external
clock)
Output delay
time
(Using internal
clock)
tCKCY(1)
tCKL(1)
I
tCKH(1)
SCK0, SCK1
Refer to figure 5.
3.15-3.85
1
tCKCY(2)
tCKL(2)
3.15-3.85
3.15-3.85
2
1/2tCYC
S
O
tCKH(2)
SCK0, SCK1
Refer to figure 5.
3.15-3.85
1/2tCYC
tCYC
tICK
3.15-3.85
0.4
S
tCKI
·SI0, SI1
·SB0, SB1
·Data set-up to
SCK0 and SCK1
·Refer to figure 5.
3.15-3.85
0.4
μ
s
tCKO(1)
·SO0, SO1
·SB0, SB1
·Data hold from
SCK0 and SCK1
·Refer to figure 5.
3.15-3.85
7/12tCYC
+1
S
tCKO(2)
·SO0, SO1
·SB0, SB1
·Data hold from
SCK0 and SCK1
·Refer to figure 5.
3.15-3.85
1/3tCYC
+1
μ
s
5. Pulse Input Conditions at Ta=0
°
C to +50
°
C, VSS=0V
Ratings
Parameter
Symbol
Pins
Conditions
VDD[V]
3.15-3.85
Min.
1
Typ.
Max.
Unit
tPIH(1)
tPIL(1)
·INT0, INT1
·INT2/T0IN
·Refer to figure 6.
·INT3/T0IN
(1/1 is selected for
noise rejection
clock.)
·Refer to figure 6.
·INT3
(1/64 is selected
for noise rejection
clock.)
·Refer to figure 6.
·RES
·Refer to figure 6.
·Interrupt acceptable
·Timer 0-countable
tPIH(2)
tPIL(2)
·Interrupt acceptable
·Timer 0-countable
3.15-3.85
2
tPIH(3)
tPIL(3)
·Interrupt acceptable
3.15-3.85
128
tCYC
High/low level
pulse width
tPIL(4)
·Reset acceptable
3.15-3.85
200
μ
s
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