參數(shù)資料
型號: LC86E7248
廠商: Sanyo Electric Co.,Ltd.
英文描述: 8-Bit Single Chip Microcontroller with 48K Byte UVEPROM(8位單片微控制器(帶48K字節(jié)紫外線可擦除EPROM))
中文描述: 8位單片機(jī)微控制器48,000字節(jié)UVEPROM(8位單片微控制器(帶48,000字節(jié)紫外線可擦除存儲器))
文件頁數(shù): 12/19頁
文件大?。?/td> 621K
代理商: LC86E7248
LC86E7248
12/19
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5-6.0
min.
0
max.
±0.2
unit
VODLS
S0 to S47
Deference voltage
to ideal value
VLCD, 2/3VLCD,
1/3VLCD
Deference voltage
to ideal value
VLCD, 2/3VLCD,
1/2VLCD, 1/3VLCD
Resistance at a
ladder resistor
Resistance at a
ladder resistor
1/2R mode
VOH=0.9VDD
LCD output
regulation
VODLC
COM0 to COM3
4.5-6.0
0
±0.2
V
RLCD(1)
4.5-6.0
60
LCD ladder
resistor
RLCD(2)
4.5-6.0
30
Pull-up MOS
Tr. resistor
Rpu
Ports 0, 1, 3
Ports A,B,C,D,E,F
Ports 70, 71, 72, 73
Port 1
Ports 70, 71, 72, 73
RES
All pins
4.5-6.0
15
40
70
k
Hysteresis
voltage
VHIS
Output disable
4.5-6.0
0.1VDD
V
Pin capacitance
CP
f=1MHz
Unmeasurement
terminals for the
input are set to
VSS level.
Ta=25
°
C
4.5-6.0
10
pF
4. Serial Input / Output Characteristics at Ta=+10
°
C to +40
°
C, VSS=VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5-6.0
min.
2
1
max.
unit
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
tCKCY(1)
tCKL(1)
I
tCKH(1)
SCK0,
SCK1
Refer to figure 5.
1
tCKCY(2)
tCKL(2)
2
1/2
tCKCY
1/2
tCKCY
S
O
tCKH(2)
SCK0,
SCK1
Use pull-up
resistor (1k
)
when open drain
output.
Refer to figure 5.
Data set-up to
SCK0, 1
Data hold from
SCK0, 1
Refer to figure 5.
4.5-6.0
tCYC
Data set up time
Data hold time
Output delay time
(Serial clock is
external clock)
Output delay time
(Serial clock is
internal clock)
tICK
4.5-6.0
0.1
S
tCKI
SI0,SI1
SB0,SB1
4.5-6.0
0.1
tCKO(1)
4.5-6.0
7/12tCYC
+0.2
S
tCKO(2)
SO0, SO1
SB0, SB1
Use pull-up
resistor (1k
)
when open drain
output.
Data hold from
SCK0, 1
Refer to figure 5.
4.5-6.0
1/3tCYC
+0.2
μ
s
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