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參數(shù)資料
| 型號： | LC866556B |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8-Bit Single Chip Microcontroller with On-Chip 56K（57344 ×8 bits）-Byte ROM and 1152（1152 ×8 bits）-Byte RAM(8位單片微控制器（帶片上56K（57344 ×8 bits）字節(jié)ROM和1152（1152 ×8 bits）字節(jié)RAM）) |
| 中文描述： | 8位單片機(jī)微控制器的片上速度56K（57344 × 8位）字節(jié)ROM和1152（1152 × 8位）字節(jié)的RAM（8位單片微控制器（帶片上速度56K（57344 × 8位）字節(jié)光盤和1152（1152 × 8位）字節(jié)的RAM）） |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 636K |
| 代理商： | LC866556B |
LC866560/56B
3/21
- Timer1
16-bit timer / PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable-bit PWM (9-16 bits)
In Mode 0 and Mode 1, the resolution of Timer and PWM is tCYC.
In Mode 2 and Mode 3, the resolution of Timer and PWM selectable ; tCYC or 1/2tCYC by program
- Base timer
Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer clock)
Every 976
μ
s, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768kHz crystal oscillation for Base timer clock)
The Base timer clock selectable ; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of
Timer 0
(9) Buzzer output
- The Buzzer sound frequency selectable ; 4KHz, 2KHz (using 32.768kHz crystal oscillation for Base timer clock)
(10) Remote control receiver circuit (Shares with the P73/INT3/T0IN terminal)
- Noise rejection function (the time constant of noise rejection filter : 1 tCYC/16 tCYC/64 tCYC)
(tCYC : instruction cycle time)
- Switch polarity function
(11) Watchdog timer
- The watchdog timer is taken on RC outside
- Watchdog timer operation selectable : interrupt system, system reset
(12) Interrupts system
- 14-sources 10-vectored interrupts :
1. External interrupt INT0 (include watchdog timer)
2. External interrupt INT1
3. External interrupt INT2, timer / counter T0L (Lower 8 bits)
4. External interrupt INT3, base timer
5. Timer / counter T0H (Upper 8-bit)
6. Timer T1L, Timer T1H
7. Serial interface SIO0
8. Serial interface SIO1
9. AD converter
10. VFD automatic display controller, Port 0
- Built-in interrupt priority control register
Microcomputer allows 3 levels of interrupt; low level, high level, and highest level of multiplex interrupt. It can
specify a low level or a high level interrupt priority from INT2/T0L through port 0 (i.e. the above interrupt number
from three through ten). It can also specify a low level or the highest level interrupt priority to INT0 and INT1.
(13) Sub-routine stack levels
- 128 levels (Max.) : stack area included in RAM area
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