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參數(shù)資料
| 型號： | LC866524A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 85 |
| 中文描述： | 四2正輸入或門 14-TSSOP封裝；-40℃到85℃ |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 641K |
| 代理商： | LC866524A |
LC866548/40/32/28/24A
No.6700-15/21
4. Serial Input/Output Characteristics at Ta=-30
°
C to +70
°
C, VSS1=VSS2=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5 - 6.0
min.
2
max.
unit
Cycle
Low Level
pulse width
High Level
pulse width
Cycle
Low Level
pulse width
High Level
pulse width
Data set up time
Data hold time
Output delay
time
(Serial clock is
external clock)
Output delay
time
(Serial clock is
internal clock)
tCKCY(1)
tCKL(1)
1
I
tCKH(1)
SCK0
SCK1
Refer to figure 5.
1
tCKCY(2)
2
tCKL(2)
1/2tCKCY
S
O
tCKH(2)
SCK0
SCK1
Use pull-up
resistor (1k
)
when open drain
output.
Refer to figure 5.
Data set-up to
SCK0, 1.
Data hold from
SCK0, 1.
Refer to figure 5.
4.5 - 6.0
1/2tCKCY
tCYC
tICK
0.1
S
tCKI
SI0 SI1
SB0 SB1
4.5 - 6.0
0.1
tCKO(1)
7/12tCYC
+0.2
S
tCKO(2)
SO0 SO1
SB0 SB1
Use pull-up
resistor (1k
)
when open drain
output.
Data hold from
SCK0, 1
Refer to figure 5.
4.5 - 6.0
1/3tCYC
+0.2
μ
s
5. Pulse Input Conditions at Ta=-30
°
C to +70
°
C, VSS1=VSS2=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
4.5 - 6.0
min.
1
max.
unit
tPIH(1)
tPIL(1)
tPIH(2)
tPIL(2)
INT0, INT1
INT2/T0IN
INT3/T0IN
(The noise
rejection clock is
select to 1/1.)
INT3/T0IN
(The noise
rejection clock is
select to 1/16.)
INT3/T0IN
(The noise
rejection clock is
select to 1/64.)
RES
Interrupt acceptable
Timer0-countable
Interrupt acceptable
Timer0-countable
4.5 - 6.0
2
tPIH(3)
tPIL(3)
Interrupt acceptable
Timer0-countable
4.5 - 6.0
32
tPIH(4)
tPIL(4)
Interrupt acceptable
Timer0-countable
4.5 - 6.0
128
tCYC
High/low level
pulse width
tPIL(5)
Reset acceptable
4.5 - 6.0
200
μ
s
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