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參數(shù)資料
| 型號(hào)： | LC866428B |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8-Bit Single Chip Microcontroller with On-Chip 28K（28672 ×8 bits）-Byte ROM and 768（768 ×8 bits）-Byte RAM(8位單片微控制器（帶片上28K（28672 ×8 bits）字節(jié)ROM和768（768 ×8 bits）字節(jié)RAM）) |
| 中文描述： | 8位單片機(jī)微控制器片過敏蛋白（28672 × 8位）字節(jié)ROM和768（768 × 8位）字節(jié)的RAM（8位單片微控制器（帶片上過敏蛋白（28672 × 8位）字光盤和768節(jié)（768 × 8位）字節(jié)的RAM）） |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 660K |
| 代理商： | LC866428B |
LC866448B/44B/40B/36B/32B/28B/24B/20B/16B/12B/08B
7/21
Pin description
Pin name
VSS1,2
VDD1,2
VP
PORT0
P00 to P07
I/O
-
-
-
I/O 8-bit input/output port
Input for port 0 interrupt
Input/output in nibble units
Input for HOLD release
15V withstand at N-channel open drain output
I/O 8-bit input/output port
Input/output can be specified in a bit unit
Other pin functions
P10 SIO0 data output
P11 SIO0 data input/bus input/output
P12 SIO0 clock input/output
P13 SIO1 data output
P14 SIO1 data input/bus input/output
P15 SIO1 clock input/output
P16 Buzzer output
P17 Timer 1 output (PWM0 output)
I/O 4-bit input/output port
Input/output in bit unit
15V withstand at N-channel open drain output
6-bit input port
Other pin functions
P70 : INT0 input/HOLD release/N-channel Tr.
output for watchdog timer
P71 : INT1 input/HOLD release input
P72 : INT2 input/timer 0 event input
P73 : INT3 input with noise filter/timer 0 event input
P74
: 32.768kHz crystal oscillation terminal XT1
P75 : 32.768kHz crystal oscillation terminal XT2
Interrupt received forms, the vector addresses
rising
falling
Function description
Option
Power pin (-) Short-circuit VSS1 to VSS2.
Power pin (+) *1
Power pin (+) for the VFD output pull-down resistor
-
-
-
Pull-up resistor :
Provided/Not provided (each nibble)
Output form :
CMOS/N-channel open drain (each bit)
Refer to Notes
PORT1
P10 to P17
Output form :
CMOS/N-channel open drain (each bit)
PORT3
P30 to P33
Output form :
CMOS/N-channel open drain (each bit)
Pull-up resistor :
Provided/Not provided
(P70,71,72,73)
*
P74
, P75 don’t have the pull-up
resistor option.
rising
&
falling
high
level
low
level
vector
INT0 enable enable disable enable enable
INT1 enable enable disable enable enable 0BH
INT2 enable enable enable disable disable 13H
INT3 enable enable enable disable disable 1BH
03H
PORT7
P70
P71 to P75
I/O
I
Continue.
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