參數(shù)資料
型號(hào): LC83025
廠商: Sanyo Electric Co.,Ltd.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processor for Karaoke Products
中文描述: 數(shù)字信號(hào)處理器的卡拉OK產(chǎn)品
文件頁數(shù): 7/15頁
文件大小: 262K
代理商: LC83025
Specifications
Absolute Maximum Ratings
at Ta = 25°C, V
SS
= 0 V
Allowable Operating Ranges
at Ta = –30 to +70°C, all V
DD
= 4.75 to 5.25 V, all V
SS
= 0 V unless otherwise specified
No. 4977-7/15
LC83025E
Parameter
Symbol
Conditions
Ratings
Unit
Note
Maximum supply voltage
V
DD
max
–0.3 to +7.0
V
V
O
1
OSC2 output
Allowed up to the
oscillator voltage.
V
Output voltage
V
O
2
V
IN
I
OP
1
I
OP
2
I
OA
1
I
OA
2
Σ
I
OA
1
Pins other than OSC2
–0.3 to V
DD
+ 0.3
–0.3 to V
DD
+ 0.3
V
Input voltage
V
Peak output current
Audio interface, external RAM interface
–2 to +4
mA
1
Microcontroller interface, P3, P4
–2 to +10
mA
2
Audio interface, external RAM interface: per pin
–2 to +4
mA
1
Microcontroller interface, P3, P4: per pin
–2 to +10
mA
2
Average output current
Total for FS384O, LRCKO, BCKO, and ASO
–10 to +10
mA
Σ
I
OA
2
Total for DWRT, DREAD, RAS, CAS, A3 to A8
and D0 to D7
–30 to +30
mA
Σ
I
OA
3
Pd max
Total for A0 to A2, SIAK, P3 and P4
–10 to +10
mA
Allowable power dissipation
Ta = –30 to +70°C
700
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
Operating supply voltage
V
DD
V
IH
1
V
IH
2
V
IH
3
V
IL
1
V
IL
2
V
IL
3
t
CYC
4.75
5.25
V
Audio interface, external RAM interface
2.4
V
4
Input high level voltage
P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5
0.7 V
DD
0.75 V
DD
V
5
RES, OSC1, microcontroller interface
V
6
Audio interface, external RAM interface
0.8
V
4
Input low level voltage
P0 to P2, SELC, SAIF, SAOF, TEST1 to TEST5
0.3 V
DD
0.25 V
DD
59.11
V
5
RES, OSC1, microcontroller interface
V
6
Instruction cycle time
58
ns
[External Clock Input Conditions]
Frequency
f
EXT
t
EXTH
t
EXTL
t
EXTR
t
EXTF
16.85
17.01
MHz
Pulse width
23
ns
23
ns
Rise time
9
ns
Fall time
9
ns
[Self-Excitation Oscillation Conditions]
Oscillator frequency
f
OSC
OSC1 and OSC2: shown in Figure 2.
44.1 kHz
×
768
×
± 0.1%
Shown in Figure 3.
33.84
33.90
MHz
Oscillator stabilization period
f
OSCS
100
ms
[Audio Data Input Conditions]
Transfer bit clock period
t
BCYC
t
BCW
t
S
t
H
354
ns
Transfer bit clock pulse width
Related to the BCKI and ASI pins. Shown in Figure 4.
100
ns
Data setup time
70
ns
Data hold time
70
ns
[Serial Input Clock Conditions]
Serial clock period
t
SCYC
t
SCW
t
SS
t
SH
t
SYH
t
SYW
480
ns
Serial clock pulse width
200
ns
Data setup time
Related to the microcontroller interface. Shown in
Figure 5. (Related to the SICK, SI and SRDY pins.)
70
ns
Data hold time
70
ns
SRDY hold time
200
ns
SRDY pulse width
200
ns
[DRAM Input Conditions]
Input data setup time
t
DSI
t
DHI
Related to external DRAM data input. Shown in Figure 6.
(Related to the CAS and D0 to D7 pins.)
20
ns
Input data hold time
0
ns
Related to the FS384I pin. Shown in Figure 1.
max: 44.1 kHz
×
384
×
1.005
min: 44.1 kHz
×
384
×
0.995
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