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參數(shù)資料
| 型號： | LC8220 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | JPEG Still Color Image Compression/Decompression LSI |
| 中文描述： | JPEG靜止彩色圖像壓縮/解壓大規(guī)模集成電路 |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 191K |
| 代理商： | LC8220 |
No. 4909-3/13
LC8220
Pin Functions
Pin No.
Symbol
I/O
Function
1
V
SS
CTLCS
—
Ground
2
I
Control bus chip select
*
2
3
CTLRD
I
Control bus read request
*
3
4
CTLWR
I
Control bus write request
*
4
5
CTLRDY
O
Control bus ready for read/write requests
*
5
6
CTLERR
O
Error interrupt request
7
CTLINT
O
Control bus interrupt request
8
CPUCTL
I
Connected CPU type setting for the control bus
*
1
9
CTLSIZE
I
Bus width selection for the control bus (0: 8 bits, 1: 16 bits)
10
V
DD
V
SS
CTLA7
—
+5 V power supply
11
—
Ground
12
I
13
CTLA6
I
14
CTLA5
I
15
CTLA4
I
Control address bus
16
CTLA3
I
17
CTLA2
I
18
CTLA1
I
19
CTLA0
I
20
V
DD
V
SS
CTLD15
—
+5 V power supply
21
—
Ground
22
I/O
23
CTLD14
I/O
24
CTLD13
I/O
25
CTLD12
I/O
Control data bus (D15 to D8 are unused if an 8-bit CPU is used.
*
7
)
26
CTLD11
I/O
27
CTLD10
I/O
28
CTLD9
I/O
29
CTLD8
I/O
30
V
DD
V
SS
CTLD7
—
+5 V power supply
31
—
Ground
32
I/O
33
CTLD6
I/O
34
CTLD5
I/O
35
CTLD4
I/O
Control data bus
36
CTLD3
I/O
37
CTLD2
I/O
38
CTLD1
I/O
39
CTLD0
I/O
40
V
DD
V
SS
CLK
—
+5 V power supply
41
—
Ground
42
I
System clock
43
CLKSEL
I
Clock divisor selection (0: no divisor, 1: divisor used)
*
6
44
RESET
I
System reset
45
TEST
I
Test mode selection (0: normal operation, 1: test mode)
*
6
46
TESTOUT
O
Test result output
*
8
47
MDD10
I/O
48
MDD9
I/O
Test mode data bus
*
7
49
MDD8
I/O
50
V
DD
V
SS
MDD7
—
+5 V power supply
51
—
Ground
52
I/O
53
MDD6
I/O
Test mode data bus
*
7
54
MDD5
I/O
Continued on next page.
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