LC7940KD / LC7941KDR
No.A0573-5/13
Pin Function
Pin No
LC7940KD
LC7941KDR
Symbol
I/O
Function
91
90
VDD
VSS
VEE
V1
86
95
87
94
Supply
LCD panel drive voltage supplies
VDD-VSS is the logic supply.
VDD-VEE is the LCD supply.
92
89
89
92
V3
88
93
V4
Supply
LCD panel drive voltage supplies
V1 and VEE are selected levels.
V3 and V4 are not-selected levels.
100
81
CP
I
Display data input clock (falling edge trigger).
99
82
CDI
I
Chip disable.
Data is read in When LOW, and not read in When HIGH.
Display data latch clock (falling edge trigger).
On the falling edge, the LCD drive signals set by the display data are output.
Serial data input.
98
83
LOAD
I
97
84
SDI
I
96
95
94
93
85
DI3
I
86
DI2
I
87
DI1
I
4-bit parallel data input pins.
Data input
SDI
DI3
DI2
DI1
In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.
LCD driver output
O8
O7
O6
O5
O4
O3
O2
O1
O80
O79
O78
O77
→
88
M
I
LCD panel drive voltage output alternation control signal.
85
96
P/S
I
Data input mode select. 4-bit parallel input when HIGH, and serial input when LOW.
82
99
CDO
O
Cascade connection pin for extension segment drivers.
Data is read out when HIGH. Goes LOW after data is read out.
Connected to the CDI input of the next chip.
LCD drive outputs.
The output drive level is determined by the display data, M signal and DISPOFF input
as shown below.
M
Q
L
L
L
H
H
L
H
H
*
*
Note* don’t care (tied HIGH or LOW)
O1 to O80 output control input pin.
When LOW, V1 is output on the O1 to O80 outputs.
See the truth table.
No connection.
1 to 80
80 to 1
O1 to O80
O
DISPOFF
H
H
H
H
L
Output
V3
V1
V4
VEE
V1
84
97
DISPOFF
I
81
91
NC
83
98
NC
90
100
NC
-