參數(shù)資料
型號: LC74950BG
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝: 6 X 6 MM, FBGA-96
文件頁數(shù): 20/37頁
文件大?。?/td> 350K
代理商: LC74950BG
LC74950BG
No.A1647-27/37
2) Digital clamp
Registers related to digital clamp control
Name
Functions
Sub address
bit width
SELYCRGB
This register switches between the YCbCr input and RGB input.
0: YCbCr, 1: RGB
0x14
1
STDLEVY
YG digital clamp levels (SELYCRGB=0: Y, SELYCRGB=1: G)
The 9-bit (0-511) YG video signals are clamped by the values determined assuming the pedestal
levels (Y: STDLEVY[5:0] + 118, G: STDLEVY[5:0]).
Setting range: Y (118-181), G (0-63)
0x14
6
STDLEVCB
CBB digital clamp levels (SELYCRGB=0: CB, SELYCRGB=1: B)
The 9-bit (0-511) CBB video signals are clamped by the value determined assuming the center level
(STDLEVCB[5:0] + 225) for CB and the pedestal level (STDLEVCB[5:0]) for B.
Setting range: CB (225-288), B (0-63)
0x15
6
STDLEVCR
CRR digital clamp levels (SELYCRGB=0: CR, SELYCRGB=1: R)
The 9-bit (0-511) CRR video signals are clamped by the value determined assuming the center level
(STDLEVCR[5:0] + 225) for CR and the pedestal level (STDLEVCR[5:0]) for R.
Setting range: CR (225-288), R (0-63)
0x16
6
DCLINE
This sets the digital clamp update unit.
0: 1V, 1: 1H (used for testing)
0x15
1
FRAMEDC
[When the digital clamp update unit is 1V (DCLINE=0)]
This register sets the number of update frames (FRAMEDC[4:0] + 1).
Setting range: 0-31 (1 to 32 frames)
0x17
5
TCDIGCLP
This register sets the digital clamp time constant.
000: 1/1
001: 1/2
010: 1/4
011: 1/8
100: 1/16
101: 1/32
110: 1/64
111: 1/128
0x17
3
Digital clamp specifications
The 9-bit (0-511) video signals output from the ADC are clamped at the set digital clamp pulse position to the set
digital clamp level.
The digital clamp level setting values are given below.
Y=118+STDLEVY[5:0]
Cb/Cr=225+(STDLEVCB[5:0]/STDLEVCR[5:0])
R, G, B=STDLEVY[5:0]/STDLEVCB[5:0]/STDLEVCR[5:0]
Pedestal level setting value
Sink tip level
Pedestal level
Input signal
Sync level
511
0
Digital clamp pulse
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