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參數(shù)資料
| 型號： | LC74783M |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 畫面疊加 |
| 英文描述： | ON-SCREEN DISPLAY IC, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 181K |
| 代理商： | LC74783M |
{ COMMAND3 (Horizontal display start position and horizontal character size setup command)
First byte
Second byte
Note: The register states are all set to zero when the LC74783/M is reset with the RST pin.
| COMMAND4 (Display control setup command)
First byte
No. 4990-10/15
LC74783, 74783M
Register content
DA0 to DA7
Register name
State
Function
Note
7
—
1
6
—
0
Command 3 identification code
5
—
1
Set the horizontal display start position and horizontal
4
—
1
character size.
3
HS21
0
1
Second line horizontal character size
2
HS20
0
1
HS11
0
1
First line horizontal character size
0
HS10
0
1
HS21
HS20
0
1
0
1 Tc per dot
2 Tc per dot
1
3 Tc per dot
1 Tc per dot
HS11
HS10
0
1
0
1 Tc per dot
2 Tc per dot
1
3 Tc per dot
1 Tc per dot
Register content
DA0 to DA7
Register name
State
Function
Note
7
—
0
Second byte identification bit
6
LC
0
An LC oscillator is used for the dot clock.
Selects the dot clock used in horizontal
1
A crystal oscillator is used for the dot clock.
character display.
5
HP5
0
If HS is the horizontal start position then:
(MSB)
1
5
4
HP4
0
HS = Tc
× (2Σ 2nHP
n)
1
n = 0
3
HP3
0
1
2
HP2
0
1
HP1
0
1
0
HP0
0
(LSB)
1
The horizontal display start position is
set by the six bits HP5 to HP0.
The weight of bit 1 is 2Tc.
Tc: Period of the oscillator connected to OSCIN/OSCOUT in
operating mode.
Register content
DA0 to DA7
Register name
State
Function
Note
7
—
1
6
—
1
Command 4 identification code
5
—
0
Display control
4
—
0
3
TSTMOD
0
Normal operating mode
This bit must be zero.
1
Test mode
0
The RAM erase operation requires about
2
RAMERS
500 s (It is executed in the DSPOFF
1
Erase display RAM (set to 7F hexadecimal)
state.)
1
OSCSTP
0
Do not stop the crystal oscillator and LC oscillator circuits.
Valid when character display is off in
1
Stop the crystal oscillator and LC oscillator circuits.
external synchronization mode.
0
SYSRST
0
Reset occurs when the CS pin is low, and
1
Reset all registers and turn the display off.
the reset is cleared when CS goes high.
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