參數(shù)資料
型號: LC7442E
元件分類: 畫面疊加
英文描述: PICTURE-IN-PICTURE IC, PQFP64
封裝: QFP-64
文件頁數(shù): 13/23頁
文件大?。?/td> 317K
代理商: LC7442E
LC7442, 7442E
Clamp Pulse
A/D converter clamp
Since clamp pulses are output with the timing shown in the figure below, it is setup to fall within the pedestal range.
On reset and during standby, the KH signal goes to a positive polarity, and is output as such.
D/A converter clamp
Digital data in the A region:
MSB
LSB
Y D/A:
0
R-Y D/A:
1
0
B-Y D/A:
1
0
Clamping is applied by the main screen horizontal synchronization signal.
External Control Output Timing
Relationship with the LC7480 A/D converter
Note: Since this circuit operates at the high speeds shown in this figure, care is required to keep leads as short as possible in the wiring used in this circuit.
No. 4412-20/22
A/D input
Notes: 1: The conditions t3 > 0 s and t4 > 0.5 s must be met.
2: The value of 4.8 s for t1 is the value when registers CLPAJ0 and 1 are 00.
D/A output
Sampling data
(LC7480 output)
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