參數(shù)資料
型號(hào)： LC7441NE
元件分類： 畫面疊加
英文描述： PICTURE-IN-PICTURE IC, PQFP64
封裝： QIP-64
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 410K
代理商： LC7441NE
LC7441N, 7441NE
No.3941–16/20
Memory Readout Range
The horizontal memory-readout range is 244 dots
comprising 122, 61 and 61 dots of Y, R – Y and B – Y
data, respectively. The NTSC and PAL vertical memory
readout ranges are 77 and 83 horizontal lines, respec-
tively, as shown in figures 6 and 7, respectively.
Sync Signals
The PCB layout should not allow noise to be induced in
the OH, OV, KH and KV signals from the sync-separator
IC because this can cause screen distortion. The sub-
screen display should be turned off when the sync signals
Figure 6. NTSC memory readout range
Figure 7. PAL memory readout range
Odd-field Decision Circuits
The OH/OV and KH/KV odd-field decision circuits
measure the phase difference between the horizontal and
vertical sync pulses as shown in the following figure.
When the field is odd, a single output horizontal sync
pulse is blanked during the vertical sync pulse period,
and when even, two are blanked. The phase difference is
measured between the falling edges of the sync pulses
when TV/VCR is HIGH, and between the rising edges,
when TV/VCR is LOW.
Note
tW > 1 s
PLLOH
The read-PLL locks to the main-screen horizontal sync
frequency when PLLOH is HIGH, and to the sub-screen
horizontal sync frequency, when PLLOH is LOW. Using
a PLL clock to generate the horizontal sync signal and
determine the sub-screen display position results in an
error-free display.
PLLOH is normally held HIGH. However, when OH is
unstable, PLLOH should be held LOW, otherwise the
PLL clock becomes unstable and the sub-screen flickers.
become unstable because the display can become dis-
torted. The OH and KH input signals should lag the
video horizontal sync signals by 1
s as shown in the
following figure.
相關(guān)PDF資料
PDF描述
LC7442 PICTURE-IN-PICTURE IC, PDIP64
LC7442E PICTURE-IN-PICTURE IC, PQFP64
LC7455A SPECIALTY CONSUMER CIRCUIT, PDIP16
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