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參數(shù)資料
| 型號： | LC74401E |
| 元件分類： | 畫面疊加 |
| 英文描述： | PICTURE-IN-PICTURE IC, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 352K |
| 代理商： | LC74401E |
Allowable Operating Ranges at Ta = –10 to +70°C, VSS = 0 V
Electrical Characteristics at Ta = 25 ± 2°C, VDD = 5 V ± 10%, VSS = 0 V
Note: 1. Test conditions as follows:
RES: VDD, V-M, V-S: 60 Hz, H-M, H-S: 15 kHz
A/D converter data: 1010..., No output load
2. There are four power supply pin systems.
The supply voltages must all be equal, i.e., DVDD = AVDD = VDD-M = VDD-S. Descriptions are in terms of VDD.
The grounds must all be equal, i.e., DVSS = AVSS = VSS-M = VSS-S. Descriptions are in terms of VSS.
Switching Characteristics at Ta = 25 ± 2°C, VDD = 5 V ± 10%, VSS = 0 V
No. 4872-14/19
LC74401E, 74402, 74402E
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Supply voltage
VDD
4.5
5.0
5.5
V
Input high level voltage
VIH1
CMOS level
0.7 VDD
V
VIH2
TTL level
2.2
V
Input low level voltage
VIL1
CMOS level
0.3 VDD
V
VIL2
TTL level
0.8
V
Reference voltage
VREF
3.4
0.8 VDD
VDD
V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Output high level voltage
VOH1
Pins CP-M and CP-S: IOH = –1 mA
VDD – 1
V
VOH2
Pins other than CP-M and CP-S: IOH = –1 mA
VDD – 1
V
VOL1
Pins CP-M and CP-S: IOL = 1 mA
1.0
V
Output low level voltage
VOL2
Pins other than CP-M and CP-S: IOL = 2 mA
0.4
V
VOL3
With the SDA pin output active: IOL = 3 mA
0.4
V
IDDD
The DVSS pin
25
mA
Operating current drain*1
IDDA
The AVSS pin
21
mA
IDDM
The VSS-M pin
2
mA
IDDS
The VSS-S pin
2
mA
Quiescent current
IDDS
RES: VSS
10
A
with DC signals on the input pins and no output load.
Input leakage current
ILK
VI = VDD, VSS
–1
+1
A
Output leakage current
IOZ
Pins CP-M and CP-S; VI = VDD, VSS
–1
+1
A
D/A converter output resistance
RDA
150
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Vertical synchronization signal
Pulse width
tVW
1
s
Rise time
tVR
50
ns
Fall time
tVF
50
ns
Horizontal synchronization signal
Pulse width
tHW
1
s
Rise time
tHR
50
ns
Fall time
tHF
50
ns
I2C timing
SCL frequency
tSCL
100
kHz
Bus release time
tBUF
4.7
s
Start hold time
tHD; STA
4.0
s
SCL low period
tLOW
4.7
s
SCL high period
tHIGH
4.0
s
Data hold time
tHD; DAT
0
s
Data setup time
tSU; DAT
250
ns
Rise time
tR
1000
ns
Fall time
tF
300
ns
Stop setup time
tSU; STO
4.0
s
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