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參數(shù)資料
| 型號： | LC74201JE |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Single Chip MPEG Decoder |
| 中文描述： | 單芯片的MPEG解碼器 |
| 文件頁數(shù)： | 4/21頁 |
| 文件大小： | 301K |
| 代理商： | LC74201JE |
Clock Pins
Microcontroller Interface
Note: AD0 to AD7 use N-channel open-drain outputs.
No. 5761-4/21
LC74201JE
Pin No.
Symbol
I/O
Logic
Function
18
FSCO
Out
Positive
Subcarrier clock output (frequency = 1/4 pixel clock frequency). Tristate output using DV
DD
2 (5-V) power
supply.
19
PCKO
Out
Positive
Pixel clock output (NTSC-4fsc, PAL-4fsc, or 13.5 MHz). Tristate output using DV
DD
1 (4-V) power supply.
61
CLKSEL
In
Positive
Clock selection control input. High: 54.0-MHz clock input from pin 62 (CLKIN); Low: clock from internal
VCO oscillator.
62
CLKIN
In
Positive
54.0-MHz clock input (with built-in bias). When not used, connect to DV
DD
1 or DV
SS
1.
55
XPALIN
In
–
Crystal oscillator connections for PAL-4fsc oscillation circuit (4fsc = 17.734475 MHz)
58
56
XNTIN
In
–
Crystal oscillator connections for NTSC-4fsc oscillation circuit (4fsc = 14.31818 MHz)
56
XPALOUT
Out
–
59
XNTOUT
Out
–
66
PLLFIL
–
–
PLL filter connection
CD-DSP clock input (16.9344, 2.8224, or 2.1168 MHz)
Adjustment resistor connection for VCO oscillator circuit.
63
VCOR
–
–
68
CDCK
In
Positive
Pin No.
Symbol
I/O
Logic
Function
44
STB (CL)
In
Positive
Parallel interface: Strobe signal input for address input and data I/O.
Serial interface: Serial transfer clock signal input.
45
AD0 (DO)
I/O
Positive
Parallel interface: Address/data I/O port P0 (LSB).
Serial interface: ZPSerial data output (LSB-first input).
43
AS/DS (CE)
In
Positive
Parallel interface: Address/data select input (Low = address).
Serial interface: Serial transfer enable signal input (High = enabled).
46
AD1 (DI)
I/O
Positive
Parallel interface: Address/data I/O port P1.
Serial interface: Serial data input (LSB-first output).
41
IRQ
Out
Negative
Interrupt request signal output (N-channel open-drain output).
Parallel interface: Address/data I/O ports.
The interface mode is determined at the release of the system reset.
The mode is determined by setting the three bits of AD3, AD4, and AD5.
Serial interface: AD5:AD4:AD3 = 1:
*
:
*
(
*
= Don’t care)
Parallel interface: AD5:AD4:AD3 = 0:1:0 or 0:1:1 or 0:0:0
AD7: Parallel interface address/data I/O port P7 (MSB).
System reset input (Hysteresis input; built-in pull-up resistor).
38
RESET
In
Negative
47
AD2
I/O
Positive
48
AD3
I/O
Positive
49
AD4
I/O
Positive
50
AD5
I/O
Positive
51
AD6
I/O
Positive
52
AD7 (MBS)
I/O
Positive
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