參數(shù)資料
型號: LC72722M
廠商: Sanyo Electric Co.,Ltd.
英文描述: Single-Chip RDS Signal-Processing System LSI
中文描述: 單芯片發(fā)展策略的信號處理系統(tǒng)LSI
文件頁數(shù): 11/15頁
文件大?。?/td> 114K
代理商: LC72722M
No. 5602-11/15
LC72722, 72722M, 72722PM
Timing 2 (mode 3, PT2 = 0)
A12378
Input data
Error correction
SYNC output
ERROR output
CORREC output
Sync NG Sync OK Sync OK Sync OK Sync OK Sync OK Sync NG Sync NG
Data
corrected
No
errors
No
errors
Data
corrected
Uncorrectable Uncorrectable
Tp1
Tp1
Serial Data Input and Output Methods
Data is input and output using the CCB (computer control bus), which is the Sanyo audio IC serial bus format. This IC
adopts an 8-bit address CCB format.
I/O mode
(LSB)
Address
(MSB)
Comment
B0
B1
B2
B3
A0
A1
A2
A3
1
IN1 (6A)
0
1
0
1
0
1
1
0
· Control data input mode, also referred to as “serial data input” mode.
· This is a 16-bit data input mode.
2
IN2 (6B)
1
1
0
1
0
1
1
0
· Control data input mode, also referred to as “serial data input” mode.
· This is a 16-bit data input mode.
3
OUT (6C)
0
0
1
1
0
1
1
0
· Data output mode, also referred to as “serial data output” mode.
· The data for multiple blocks can be output sequentially in this mode.
CE
CL
DI
DO
B0
B1
B2
B3
A0
A1
A2
A3
First Data IN1/2
First Data OUT
First Data OUT
A12379
1
1
2
1
2
2
I/O mode determined
For the CL normal high state
For the CL normal low state
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