參數(shù)資料
型號(hào): LC72720YV
廠商: Sanyo Electric Co.,Ltd.
英文描述: Single-Chip RDS Signal-Processing System IC(單片無(wú)線電數(shù)據(jù)系統(tǒng)信號(hào)處理芯片)
中文描述: 單芯片發(fā)展策略的信號(hào)處理系統(tǒng)集成電路(單片無(wú)線電數(shù)據(jù)系統(tǒng)信號(hào)處理芯片)
文件頁(yè)數(shù): 5/14頁(yè)
文件大?。?/td> 107K
代理商: LC72720YV
No. 6488-5/14
LC72720Y, 72720YV
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
Group delay deviation
G-Delay
FLOUT: f = 57
±
1.2 kHz
±
2.0
μs
Reference voltage output
Vref
VREF : Vdda = 3.3 V
1.65
V
Hysteresis
V
HIS
V
OL
1
V
OL
2
I
IH
1
I
IH
2
I
IL
1
I
IL
2
CL, DI, CE, SYR, T1, T2
0.1 Vddd
V
Output low-level voltage
DO, T3, T4, T5, T6, T7 : I = 2 mA
0.5
V
SYNC, RDS-ID : I = 8 mA
0.5
V
Input high-level current
CL, DI, CE, SYR, T1, T2 : V
I
= Vddd
XIN : V
I
= Vddd
CL, DI, CE, SYR, T1, T2 : V
I
= 0 V
XIN : V
I
= 0 V
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7 :
V
O
= 6.5 V
Vddd + Vdda, Vddd = Vdda = 3.3 V
5.0
μA
0.9
4.0
μA
Input low-level current
5.0
μA
0.9
4.0
μA
Output off leakage current
I
OFF
5.0
μA
Current drain
IDD
6
mA
Continued from preceding page.
CCB Output Data Format
Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.
Any number of 32-bit output data blocks can be output consecutively.
When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data
consecutively.
If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted.
However, if only the last bit is remaining to be read, it will not be possible to reread that whole block.
The check bits (10 bits) are not output.
The data valid / invalid decision is made by referencing the error information flag (E0 to E2) but the offset word
detection flag (OWD) must not be referred to.
When the first leading bits are not “1010”, the read in data is invalid, and the read operation is cancelled.
(1) Offset word detection flag (1 bit): OWD
OWD
Offset word detection
1
Detected
0
Not detected (protection function operating)
DI
DO
A13207
0
1
0
1
0
OWD
B2 B1 B0 RE
RF1 RF0 ARI SYC
E2 E1 E0
D15 D14 D13 D12 D11 D10
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
B1
B0
1
B2
1
B3
0
A0
1
A1
1
A2
0
A3
CCB address 6C
Output data/first bit
Last bit
(8) RDS data
(7) Error information flags
(6) Synchronization established flag
(5) ARI (SK) detection flag
(4) RAM data remaining flags
(3) Consecutive RAM read out possible flag
(2) Offset word information flags
(1) Offset word detection flag
Fixed pattern (1010)
相關(guān)PDF資料
PDF描述
LC72720 Single-Chip RDS Signal-Processing System LSI
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參數(shù)描述
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