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參數(shù)資料
| 型號： | LC72711LW |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 10 X 10 MM, SQFP-64 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大小： | 157K |
| 代理商： | LC72711LW |
LC72711W, 72711LW
No.6167-12/26
Data Update Timing for Read Registers
The data in the two read registers (the status register at address 01H and the block number register at address 02H) is
updated in the 1 ms interval between 1 ms prior to the output of the interrupt control signal (INT) and a point
immediately before the INT output.
In normal processing, when an interrupt occurs, the application will first determine the nature of the data packet that
will be output by the current interrupt signal by reading out the status register, and determine if it is necessary to read
out that data. For example, if error correction failed and the erroneous data is not required, the application should
simply wait for the next interrupt.
If the CCB interface is used, the application reads out the data from CCB address #FB, and determines the status from
the additional 16 bits of data. It then either reads out the following data or sets the CE signal low to cancel the readout.
Applications can also read out data asynchronously with respect to the interrupt signal. In this case, the application
checks the current reception status by reading out the status register and checking bit 6 (data received in the block
synchronized state) and bit 5 (data received in the frame synchronized state). In this case, using data for which bit 7
(VH) is 0 provides superior real time characteristics.
CPU Interface Timing <Parallel Mode>
Register Read Timing
* tHARD stipulates the earliest timing for A0 to A3 and CS.
CS
RD
RDY
A0 to A3
tSARD
tDRDY
tWRDY
tWRDL1, tWRDL2
tCYRD
tHARD
tRDH
VALID
OUTPUT
DATn
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