參數(shù)資料
型號: LC72346
廠商: Sanyo Electric Co.,Ltd.
英文描述: Ultralow-Voltage ETR Controller with On-Chip LCD Driver
中文描述: 超低電壓東突控制器的片上LCD驅(qū)動器
文件頁數(shù): 11/12頁
文件大?。?/td> 95K
代理商: LC72346
No. 6651-11/12
LC72346W, 72347W
Continued from preceding page.
Mnemonic
Operand
Function
Operations function
Instruction format
1st
2nd
AND
r
M
AND M with r
R
(r) AND (M)
M
(M) AND I
R
(r) OR (M)
M
(M) OR I
R
(r) XOR (M)
M
(M) XOR I
carry
(r)
ANDI
M
I
AND I with M
OR
r
M
OR M with r
ORI
M
I
OR I with M
EXL
r
M
Exclusive OR M with r
EXLI
M
I
Exclusive OR M with M
SHR
r
Shift r right with carry
LD
r
M
Load M to r
R
(M)
M
(r)
ST
M
r
Store r to M
MVRD
r
M
Move M to destination M
referring to r in the same row
[DH, Rn]
(M)
MVRS
M
r
Move source M referring to r
to M in the same row
M
[DH, Rn]
MVSR
M1
M2
Move M to M in the same row
[DH, DL1]
[DH, DL2]
M
I
MVI
M
I
Move I to M
TMT
M
N
Test M bits, then skip if all bits
specified are true
if M (N) = all 1, then skip
TMF
M
N
Test M bits, then skip if all bits
specified are false
if M (N) = all 0, then skip
JMP
ADDR
Jump to the address
PC
ADDR
PC
ADDR
Stack
(PC) + 1
PC
Stack
PC
Stack,
BANK
Stack,
CARRY
Stack
(Status W-reg) N
1
(Status W-reg) N
0
If (Status R-reg) N = all 1,
then skip
CAL
ADDR
Call subroutine
RT
Return from subroutine
RTI
Return from interrupt
SS
SWR
N
Set status register
RS
SWR
N
Reset status register
TST
SRR
N
Test status register true
TSF
SRR
N
Test status register false
If (Status R-reg) N = all 0,
then skip
TUL
N
Test Unlock F/F
If Unlock F/F (N) = All 0,
then skip
PLL reg
PLL data
SIO reg
I1, I2
UCCW1
I
UCCW2
I
BEEP reg
I
DZC reg
I
Timer reg
I
IOS reg PWn
N
M
(Pn)
Pn
M
M
(Pn reg)
PLL
M
Load M to PLL register
SIO
I1
I2
Serial I/O control
UCS
I
Set I to UCCW1
UCC
I
Set I to UCCW2
BEEP
I
Beep control
DZC
I
Dead zone control
TMS
I
Set timer register
IOS
PWn
N
Set port control word
IN
M
Pn
Input port data to M
OUT
M
Pn
Output contents of M to port
INR
M
Rn
Input register/port data to M
OUTR
M
Rn
Output contents of M to
register/port
Rn reg
(M)
SPB
N
Set port1 bits
(Pn)N
1
(Pn)N
0
RPB
N
Reset port1 bits
TPT
N
Test port1 bits, then skip if all bits If (Pn)N = all 1, then skip
TPF
N
Test port1 bits, then skip if all bits If (Pn)N = all 0, then skip
BANK
I
Select Bank
BANK
I
f
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
DH
DL
r
0
0
1
0
0
1
DH
DL
I
0
0
1
0
1
0
DH
DL
r
0
0
1
0
1
1
DH
DL
I
0
0
1
1
0
0
DH
DL
r
0
0
1
1
1
0
DH
DL
I
0
0
0
0
0
0
0
0
1
1
1
0
r
1
1
0
1
0
0
DH
DL
r
1
1
0
1
0
1
DH
DL
r
1
1
0
1
1
0
DH
DL
r
1
1
0
1
1
1
DH
DL
r
1
1
1
0
0
0
DH
DL1
DL2
1
1
1
0
0
1
DH
DL
I
1
1
1
1
0
0
DH
DL
N
1
1
1
1
0
1
DH
DL
N
1
0
0
ADDR (13 bits)
1
0
1
ADDR (13 bits)
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
1
1
1
1
0
0
0
SWR
N
1
1
1
1
1
1
1
1
0
0
1
SWR
N
1
1
1
1
1
1
1
1
0
1
SRR
N
1
1
1
1
1
1
1
1
1
0
SRR
N
0
0
0
0
0
0
0
0
1
1
0
1
N
1
1
1
1
1
0
DH
DL
r
0
0
0
0
0
0
0
1
I1
I2
0
0
0
0
0
0
0
0
0
0
0
1
I
0
0
0
0
0
0
0
0
0
0
1
0
I
0
0
0
0
0
0
0
0
0
1
1
0
I
0
0
0
0
0
0
0
0
1
0
1
1
I
0
0
0
0
0
0
0
0
1
1
0
0
I
1
1
1
1
1
1
1
0
PWn
N
1
1
1
0
1
0
DH
DL
Pn
1
1
1
0
1
1
DH
DL
Pn
0
0
1
1
1
0
DH
DL
Pn
0
0
1
1
1
1
DH
DL
Rn
0
0
0
0
0
0
1
0
Pn
N
0
0
0
0
0
0
1
1
Pn
N
1
1
1
1
1
1
0
0
Pn
N
1
1
1
1
1
1
0
1
Pn
N
0
0
0
0
0
0
0
0
0
1
1
1
I
B
i
J
c
L
T
Continued on next page.
I
g
B
i
S
i
I
H
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