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參數(shù)資料
| 型號(hào)： | LC72136N |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | PLL Frequency Synthesizer for Electronic Tuning(用于電子調(diào)諧的鎖相環(huán)頻率合成器) |
| 中文描述： | 鎖相環(huán)頻率合成器電子調(diào)諧（用于電子調(diào)諧的鎖相環(huán)頻率合成器） |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 319K |
| 代理商： | LC72136N |
No. 5608-7/23
LC72136N, 72136NM
Continued from preceding page.
Pin No.
Symbol
(MFP pin numbers
are in parentheses.)
Type
Functions
Circuit configuration
7 (8)
8 (9)
9 (10)
10 (11)
14 (15)
2 (3)
11 (12)
13 (14)
18 (19)
19 (20)
20 (21)
12 (13)
BO1
BO2
BO3
BO4
BO5
BOF
IO1
IO2
PD
AIN
AOUT
IFIN
Output ports
Input or output
ports
Charge pump
output
LPF amplifier
transistor
connections
IF counter
Dedicated outputs
The output states are determined by the BO1 to BO5
bits in the serial data.
Data: 0 = open, 1= low
A time base signal (8 Hz) can be output from the BO1
pin. (When the serial data TBC bit is set to 1.)
Care is required when using the BO1 pin, since it has a
higher on impedance that the other output ports (pins
BO2 to BO5).
The output state of the BOF pin is determined by the
serial data DVS bit. Thus this pin can be used as an FM
band selection switch. (Note that it should not be used
as an AM band selection switch since it is susceptible to
noise from the crystal oscillator.)
DVS data: 0 = open, 1 = low
All output ports are set to the open state following a
power on reset.
I/O dual-use pins
The direction (input or output) is determined by bits IOC1
and IOC2 in the serial data.
Data: 0 = input port, 1 = output port
When specified for use as input ports:
The state of the input pin is transmitted to the controller
over the DO pin.
Input state: low = 0 data value
high = 1 data value
When specified for use as output ports:
The output states are determined by the IO1 and IO2
bits in the serial data.
Data: 0 = open, 1 = low
These pins function as input pins following a power on
reset.
PLL charge pump output
When the frequency generated by dividing the local
oscillator signal frequency by N is higher than the
reference frequency, a high level is output from the PD
pin. Similarly, when that frequency is lower, a low level is
output. The PD pin goes to the high-impedance state
when the frequencies match.
The n-channel MOS transistor used for the PLL active
low-pass filter.
Accepts an input in the frequency range 0.4 to 12 MHz.
The input signal is directly transmitted to the IF counter.
The result is output starting the MSB of the IF counter
using the DO pin.
Four measurement periods are supported: 4, 8, 32, and
64 ms.
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