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參數(shù)資料
| 型號： | LC72131KM |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | 0.300 INCH, MFP-20 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 200K |
| 代理商： | LC72131KM |
LC72714W
No.6871-15/29
Structure of the Post-Correction Output Data <CCB Interface>
Post-error correction data can be output by using CCB address #FB. Although there are up to 288 bits of valid data that
can be output, it is possible to stop clock input (CL input) and set CE to the low level, and output the remaining data on
the next interrupt with no harmful effects whatsoever.
The maximum amount of data that can be output is 288 bits (36 bytes), and the contents of the status register (STAT)
and the block number register (BLNO) are added as the first two bytes.
The contents of the STAT and BLNO registers are output LSB first.
The post-correction data is output in order starting with the first bit in each single block of data.
The BIC code is not output.
The values of the output data are not guaranteed if multiple data read operations are performed for a single interrupt
signal (INT).
STAT (8 bits)
BLNO (8 bits)
Data section (176 bits) Post-error correction data
Layer 2 CRC (14 bits)
Parity (82 bits)
DO0 to DO7
DO8 to DO15
DO16 to DO191
DO192 to DO205
DO206 to DO287
Layer 4 CRC Check Circuit <CCB Interface>
The basic outline of this operation is the same as that described in the Layer 4 CRC Detection Circuit <Parallel
Interface> section earlier in this document. The data group data used for this error detection operation is sent to the IC
using the CCB interface. The value #FC is used as the CCB address.
The data group data is transferred in 8-bit units. There is no upper limit on the amount of data that can be transferred
(the value N in the figure below), and the data transfer may be divided into multiple operations.
Register Output
The IC internal status and block number registers are special-purpose registers that can be read out by applications. (See
the discussion of the read register data update timing on page 11.)
The application inputs the CCB address #FD to DI. The status register data is output first followed by the block number
register data.
A3
N
N-1
N-2
CR2
CR1
CR0
A2
A1
A0
B3
B2
B1
B0
DI
CL
CE
CRC4 pin output
Note: The number of items, N, refers to
the number of 8-bit items.
CRC4 pin output after N items
have been transferred.
tCRC
tEH
tES
tEL
tCH
tCL
tHD
tSU
A3
BLN7
BLN6
BLN5
ST2
ST1
ST0
A2
A1
A0
B3
B2
B1
B0
DI
DO
CL
CE
tSU
tHD
tCH
tCL
tES
tEL
tDDO
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72131KMA | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
| LC72131KMA-AE | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC72131M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer |
| LC72131MDTRM | 制造商:Panasonic Industrial Company 功能描述:IC |
| LC72132 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer |
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