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參數(shù)資料
| 型號(hào)： | LC7185-8750 |
| 廠(chǎng)商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類(lèi)： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 30 MHz, PDIP30 |
| 封裝： | SDIP-30 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 152K |
| 代理商： | LC7185-8750 |
(3) Timing Requirements for Hold Mode
VDD must remain at 5.0 V or higher (crystal oscillator requirement) for 6.0 ms (t HOLD) after the HOLD line is asserted (HOLD
=0(<0.3 VDD). After this, VDD may go as low as 3.2 V.
There are no constraints on timing for the HOLD and VDD pins when the chip is leaving hold mode.
The signal can be activated in one of two orders.
If HOLD is already deactivated (> 0.7 VDD), the LC7185-8750 leaves hold mode within 2.0 ms after VDD rises to >5.0 V.
If VDD is > 5.0 V, the LC7185-8750 enters normal mode within 2.0 ms after HOLD is deactivated.
(4) Reset Timing
1.
Reset timing (e.g. battery replacement)
Note: tINIT should be greater than 1.0 s.
2.
Reset caused by a sudden voltage (VDD) drop
If VDD drops momentarily down to less than 3.2 V and rises up to more than 5.0 V t > tINIT (t > 1.0 s), a reset may be
generated.
pin
Normal mode
Hold mode
Normal mode
pin
LC7185-8750
No. 3356-10/12
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