參數(shù)資料
型號: LC5768MV-5F256C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 48/99頁
文件大小: 0K
描述: IC XPLD 768MC 5NS 256FPBGA
標(biāo)準(zhǔn)包裝: 90
系列: ispXPLD® 5000MV
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 5.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 24
宏單元數(shù): 768
輸入/輸出數(shù): 193
工作溫度: 0°C ~ 90°C
安裝類型: 表面貼裝
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
包裝: 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
48
Switching Test Conditions
Figure 21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 14.
Figure 21. Output Test Load, LVTTL and LVCMOS Standards
Table 14. Test Fixture Required Components
Test Condition
R1
R2
CL
Timing Ref.
VCCO
Default LVCMOS 1.8 I/O (L -> H, H -> L)
106
35pF
VCCO/2
1.8V
LVCMOS I/O (L -> H, H -> L)
35pF
LVCMOS3.3 = 1.5V
LVCMOS3.3 = 3.0V
LVCMOS2.5 = VCCO/2
LVCMOS2.5 = 2.3V
LVCMOS1.8 = VCCO/2
LVCMOS1.8 = 1.65V
Default LVCMOS 1.8 I/O (Z -> H)
106
35pF
VCCO/2
1.65V
Default LVCMOS 1.8 I/O (Z -> L)
106
35pF
VCCO/2
1.65V
Default LVCMOS 1.8 I/O (H -> Z)
106
5pF
VOH - 0.15
1.65V
Default LVCMOS 1.8 I/O (L -> Z)
106
5pF
VOL + 0.15
1.65V
Note: Output test conditions for all other interfaces are determined by the respective standards.
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DEVICES
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