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參數(shù)資料
| 型號(hào)： | LC5768MC-5F484C |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| 中文描述： | EE PLD, 6 ns, PBGA484 |
| 封裝： | FPBGA-484 |
| 文件頁(yè)數(shù)： | 30/92頁(yè) |
| 文件大?。?/td> | 378K |
| 代理商： | LC5768MC-5F484C |
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Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
30
f
MAX
(RAM)
5
Clock Frequency to RAM in:
Single Port Mode
Dual Port Mode
Pseudo Dual Port Mode
Clock Frequency to FIFO
Power-on Time
—
—
—
—
—
155
155
180
225
200
—
—
—
—
—
155
155
180
220
200
—
—
—
—
—
155
155
160
210
200
—
—
—
—
—
155
155
160
210
200
—
—
—
—
—
93
93
106
132
200
MHz
MHz
MHz
MHz
μs
f
MAX
(FIFO)
5
t
PWR_ON
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate timing for other standards.
2. Measured using standard switching circuit, global routing loading of 1, worst case PTSA loading and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
5. CAM, FIFO, RAM f
MAX
speci
fi
cation used shared PT Clk.
ispXPLD 5000MX Family External Switching Characteristics (Continued)
Over Recommended Operating Conditions
Parameter
Description
-4
-45
-5
-52
-75
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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| LC5768MC-5F484I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5768MC-5F672C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5768MC-5F672I | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
| LC5768MC-5FN208C | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family |
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