參數(shù)資料
型號： LC5512MV-75F256C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 49/99頁
文件大?。?/td> 0K
描述： IC XPLD 512MC 7.5NS 256FPBGA
標準包裝： 90
系列： ispXPLD® 5000MV
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目： 16
宏單元數(shù)： 512
輸入/輸出數(shù)： 193
工作溫度： 0°C ~ 90°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-FPBGA（17x17）
包裝： 托盤
Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
49
Signal Descriptions
Signal Names
Descriptions
TMS
Input – This pin is the Test Mode Select input, which is used to control the IEEE 1149.1
state machine.
TCK
Input – This pin is the Test Clock input pin, used to clock the IEEE 1149.1 state
machine.
TDI
Input – This pin is the IEEE 1149.1 Test Data in pin, used to load data.
TDO
Output – This pin is the IEEE 1149.1 Test Data out pin used to shift data out.
TOE
Input – Test Output Enable pin. TOE tristates all I/O pins when driven low.
GOE0, GOE1
Input – Global output enable inputs.
RESET
Input – This pin resets all the registers in the device. The global polarity for this pin is
selectable on a global basis. The default is active low. An external pull-down is
required when polarity is set to active high.
yzz
Input/Output – These are the general purpose I/O used by the logic array.
y is the MFB
reference (alpha) and z is the macrocell reference (numeric)
y: A-X (768 macrocells)
y: A-P (512 macrocells)
y: A-H (256 macrocells)
z: 0-31
GND
GND – Ground
NC
No connect
VCC
VCC – The power supply pins for core logic.
VCCO0, VCCO1, VCCO2, VCCO3
VCC – The power supply pins for I/O banks 0, 1, 2, and 3.
VREF0, VREF1, VREF2, VREF3
Input – This pin defines the reference voltage for I/O banks 0, 1, 2, and 3.
GCLK0, GCLK1, GCLK2, GCLK3
Input – Global clock/clock enable inputs (see Figure 14 for differential pairing).
CLK_OUT0, CLK_OUT1
Output – Optional clock output from PLL 0 and 1.
PLL_RST0, PLL_RST1
Input – Optional input resets the M divider in PLL 0 and 1.
PLL_FBK0, PLL_FBK1
Input – Optional feedback input for PLL 0 and 1.
GNDP
GND – Ground for PLLs.
VCCP
VCC – The power supply pin for PLLs.
VCCJ
VCC – The power supply for the IEEE 1149.1 interface.
DATA
x
I/O – sysCONFIG data pins, bit
x.
CSB
Input – sysCONFIG interface chip select. Drive low to select sysCONFIG interface.
CFG0
Input – Defines SRAM configuration mode. Low: sysCONFIG port, high: E
2CMOS or
IEEE 1149.1 TAP.
PROGRAMB
Input – Controls the programming of SRAM. Hold high for normal operation. Toggle low
to reload SRAM from E
2 memory.
CCLK
1
Input – Clock for sysCONFIG interface. Reads and writes occur on the rising edge of
the clock.
READ
1
Input – Drive high to perform reads from the sysCONFIG interface.
INITB
I/O – Indicates status of configuration. Can be driven low to inhibit configuration.
DONE
Output (open drain) – Indicates status of configuration.
1. These inputs should not toggle during power up for proper power-up configuration.
SELECT
DEVICES
DISCONTINUED
相關(guān)PDF資料
PDF描述
MIC37252BU IC REG LDO ADJ 2.5A TO-263
171-009-203L001 CONN DB9 FEMALE SLD CUP NICKEL
LC5512MB-75F256C IC XPLD 512MC 7.5NS 256FPBGA
ISPLSI 1048E-70LTN IC PLD ISP 96I/O 15NS 128TQFP
EBC05DRYH CONN EDGECARD 10POS DIP .100 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC5512MV-75F256I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5512MV-75F484C 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5512MV-75F484I 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM EXPANDED LOG RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC5512MV-75F672C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
LC5512MV-75F672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD⑩ Family
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*