參數(shù)資料
型號(hào): LC4256V-3F256BC
廠商: LATTICE SEMICONDUCTOR CORP
元件分類: PLD
英文描述: 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
中文描述: EE PLD, 3 ns, PBGA256
封裝: FPBGA-256
文件頁數(shù): 12/74頁
文件大?。?/td> 255K
代理商: LC4256V-3F256BC
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
12
LVTTL
LVCMOS 3.3
LVCMOS 2.5
LVCMOS 1.8
3.3V PCI Compatible
All of the I/Os and dedicated inputs have the capability to provide a bus-keeper latch, Pull-up Resistor or Pull-down
Resistor. A fourth option is to provide none of these. The selection is done on a global basis. The default in both
hardware and software is such that when the device is erased or if the user does not specify, the input structure is
con
fi
gured to be a Pull-up Resistor.
Each ispMACH 4000 device I/O has an individually programmable output slew rate control bit. Each output can be
individually con
fi
gured for the higher speed transition (~3V/ns) or for the lower noise transition (~1V/ns). For high-
speed designs with long, unterminated traces, the slow-slew rate will introduce fewer re
fl
ections, less noise and
keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be
used to achieve the highest speed. The slew rate is adjusted independent of power.
Global OE Generation
Most ispMACH 4000 family devices have a 4-bit wide Global OE Bus, except the ispMACH 4032 device that has a
2-bit wide Global OE Bus. This bus is derived from a 4-bit internal global OE PT bus and two dual purpose I/O or
GOE pins. Each signal that drives the bus can optionally be inverted.
Each GLB has a block-level OE PT that connects to all bits of the Global OE PT bus with four fuses. Hence, for a
256-macrocell device (with 16 blocks), each line of the bus is driven from 16 OE product terms. Figures 9 and 10
show a graphical representation of the global OE generation.
Figure 9. Global OE Generation for All Devices Except ispMACH 4032
Shared PTOE
(Block 0)
Shared PTOE
(Block n)
Global
Fuses
GOE (0:3)
to I/O cells
Internal Global OE
PT Bus
(4 lines)
4-Bit
Global OE Bus
Global OE
Fuse connection
Hard wired
相關(guān)PDF資料
PDF描述
LC4256V-3T144C 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-5F256BC 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-5F256BI 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-5T144C 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-5T144I 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC4256V-3F256BC1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-3FN256AC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4256V-3FN256AC1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-3FN256BC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4256V-3FN256BC1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs