參數(shù)資料
型號： LC4256V-10F256BI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
中文描述： EE PLD, 10 ns, PBGA256
封裝： FPBGA-256
文件頁數(shù)： 24/74頁
文件大小： 255K
代理商： LC4256V-10F256BI
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
24
ispMACH 4032Z External Switching Characteristics
1
Over Recommended Operating Conditions
Parameter
t
PD
t
PD_MC
t
S
t
ST
t
SIR
t
SIRZ
t
H
t
HT
t
HIR
t
HIRZ
Description
2, 3, 4
-35
-5
-75
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
—
—
2.2
2.5
1.0
2.0
0.0
0.0
1.0
0.0
Max.
3.5
4.4
—
—
—
—
—
—
—
—
Min.
—
—
3.0
3.2
1.2
2.2
0.0
0.0
1.0
0.0
Max.
5.0
5.5
—
—
—
—
—
—
—
—
Min.
—
—
4.5
4.7
1.7
2.7
0.0
0.0
1.0
0.0
Max.
7.5
8.0
—
—
—
—
—
—
—
—
5-PT bypass combinatorial propagation delay
20-PT combinatorial propagation delay through macrocell
GLB register setup time before clock
GLB register setup time before clock with T-type register
GLB register setup time before clock, input register path
GLB register setup time before clock with zeto hold
GLB register hold time after clock
GLB register hold time after clock with T-type register
GLB register hold time after clock, input register path
GLB register hold time after clock, input register path with
zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output enable/disable
Input to output global product term output enable/disable
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low transparent) or high (for high
transparent)
Input register clock width, high or low
Clock frequency with internal feedback
clock frequency with external feedback, [1/(tS + tCO)]
t
CO
t
R
t
RW
t
PTOE/DIS
t
GPTOE/DIS
t
GOE/DIS
t
CW
t
GW
—
—
1.5
—
—
—
1.0
1.0
3.0
5.0
—
7.0
6.5
4.5
—
—
—
—
2.0
—
—
—
2.2
2.2
3.4
6.3
—
8.0
8.0
5.0
—
—
—
—
4.0
—
—
—
3.3
3.3
4.5
9.0
—
9.0
9.0
7.0
—
—
ns
ns
ns
ns
ns
ns
ns
ns
t
WIR
f
MAX
t
MAX
(Ext.)
1.0
267
192
—
—
—
2.2
200
156
—
—
—
3.3
150
111
—
—
—
ns
MHz
MHz
5
1. Preliminary information.
2. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
3. Measured using standard switching GRP loading of 1 and 1 output switching.
4. Pulse widths and clock widths less than minimum will cause unknown behavior.
5. Standard 16-bit counter using GRP feedback.
相關(guān)PDF資料
PDF描述
LC4256V-10T144I 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-3F256BC 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-3T144C 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-5F256BC 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-5F256BI 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LC4256V-10F256BI1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-10FN256AI 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4256V-10FN256AI1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
LC4256V-10FN256BI 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4256V-10FN256BI1 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs
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