- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377609 > LC4256C-3F256BC (LATTICE SEMICONDUCTOR CORP) 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs PDF資料下載
參數(shù)資料
| 型號(hào)： | LC4256C-3F256BC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| 中文描述： | EE PLD, 3 ns, PBGA256 |
| 封裝： | FPBGA-256 |
| 文件頁(yè)數(shù)： | 23/74頁(yè) |
| 文件大?。?/td> | 255K |
| 代理商： | LC4256C-3F256BC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)當(dāng)前第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
23
ispMACH 4000V/B/C External Switching Characteristics (Cont.)
Over Recommended Operating Conditions
Parameter
t
PD
t
PD_MC
t
S
t
ST
t
SIR
t
SIRZ
t
H
t
HT
t
HIR
Description
1, 2, 3
-5
-75
-10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
—
—
3.0
3.2
1.2
2.2
0.0
0.0
1.0
Max.
5.0
5.5
—
—
—
—
—
—
—
Min.
—
—
4.5
4.7
1.7
2.7
0.0
0.0
1.0
Max.
7.5
8.0
—
—
—
—
—
—
—
Min.
—
—
5.5
5.5
1.7
2.7
0.0
0.0
1.0
Max.
10.0
10.5
—
—
—
—
—
—
—
5-PT bypass combinatorial propagation delay
20-PT combinatorial propagation delay through macrocell
GLB register setup time before clock
GLB register setup time before clock with T-type register
GLB register setup time before clock, input register path
GLB register setup time before clock with zero hold
GLB register hold time after clock
GLB register hold time after clock with T-type register
GLB register hold time after clock, input register path
GLB register hold time after clock, input register path with
zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output enable/disable
Input to output global product term output enable/disable
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low transparent) or high (for
high transparent)
Input register clock width, high or low
Clock frequency with internal feedback
f
MAX
(Ext.) Clock frequency with external feedback, [1/ (t
S
+ t
CO
)]
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
t
HIRZ
0.0
—
0.0
—
0.0
—
ns
t
CO
t
R
t
RW
t
PTOE/DIS
t
GPTOE/DIS
t
GOE/DIS
t
CW
—
—
2.0
—
—
—
2.2
3.40
6.30
—
7.00
9.00
5.00
—
—
—
4.0
—
—
—
3.3
4.5
9.0
—
9.0
10.3
7.0
—
—
—
4.0
—
—
—
4.0
6.0
10.5
—
10.5
12.0
8.0
—
ns
ns
ns
ns
ns
ns
ns
t
GW
2.2
—
3.3
—
4.0
—
ns
t
WIR
f
MAX
2.2
227
156
—
—
—
3.3
168
111
—
—
—
4.0
125
86
—
—
—
ns
MHz
MHz
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC4256C-5F256BC | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256C-5F256BI | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256C-75F256BC | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256C-75F256BI | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256V-10F256BI | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC4256C-3F256BC1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256C-3FN256AC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC4256C-3FN256AC1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
| LC4256C-3FN256BC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| LC4256C-3FN256BC1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。