參數(shù)資料
型號: LC4128C-75T128I
文件頁數(shù): 18/57頁
文件大小: 1078K
代理商: LC4128C-75T128I
Lattice Semiconductor
ispMACH 4000V/B/C Family Data Sheet
18
ispMACH 4000V/B/C External Switching Characteristics
Over Recommended Operating Conditions
Parameter
Description
1, 2, 3
-25
-27
-3
-35
Units
ns
Min.
Max.
2.5
Min.
Max.
2.7
Min.
Max.
3.0
Min.
Max.
3.5
t
PD
5-PT bypass combinatorial propagation
delay
20-PT combinatorial propagation delay
through macrocell
GLB register setup time before clock
GLB register setup time before clock
with T-type register
GLB register setup time before clock,
input register path
GLB register setup time before clock
with zero hold
GLB register hold time after clock
GLB register hold time after clock with
T-type register
GLB register hold time after clock, input
register path
GLB register hold time after clock, input
register path with zero hold
GLB register clock-to-output delay
External reset pin to output delay
External reset pulse duration
Input to output local product term output
enable/disable
Input to output global product term out-
put enable/disable
Global OE input to output enable/disable
Global clock width, high or low
Global gate width low (for low transpar-
ent) or high (for high transparent)
Input register clock width, high or low
Clock frequency with internal feedback
Clock frequency with external feedback,
[1/ (t
S
+ t
CO
)]
t
PD_MC
3.2
3.5
3.8
4.2
ns
t
S
1.8
2.0
1.8
2.0
2.0
2.2
2.0
2.2
ns
ns
t
ST
t
SIR
0.7
1.0
1.0
1.0
ns
t
SIRZ
1.7
2.0
2.0
2.0
ns
t
H
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
ns
ns
t
HT
t
HIR
0.9
1.0
1.0
1.0
ns
t
HIRZ
0.0
0.0
0.0
0.0
ns
t
CO
t
R
t
RW
1.5
2.2
3.5
4.0
1.5
2.7
4.0
4.5
1.5
2.7
4.4
5.0
1.5
2.7
4.5
-
5.5
ns
ns
ns
t
PTOE/DIS
ns
t
GPTOE/DIS
5.0
6.5
8.0
8.0
ns
t
GOE/DIS
t
CW
1.1
1.1
3.0
1.3
1.3
3.5
1.3
1.3
4.0
1.3
1.3
4.5
ns
ns
t
GW
ns
t
WIR
f
MAX
1.1
400
250
1.3
333
222
1.3
322
212
1.3
322
212
ns
MHz
4
f
MAX
(Ext.)
MHz
Timing v.3.1
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching circuit, assuming GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
相關PDF資料
PDF描述
LC4128V-10T100I
LC4128V-10T128I
LC4128V-5T100C
LC4128V-5T100I
LC4128V-5T128C
相關代理商/技術參數(shù)
參數(shù)描述
LC4128C-75TN100C 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4128C-75TN100I 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4128C-75TN128C 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4128C-75TN128I 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4128V-10T100I 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100