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    參數(shù)資料
    

    


    


    
型號(hào)：
LC4064ZC-5M132C1

    

    
廠商：
Lattice Semiconductor Corporation

    

    
英文描述：
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs

    

    
中文描述：
3.3V/2.5V/1.8V在系統(tǒng)可編程超快高密度PDLs

    

    
文件頁數(shù)：
13/91頁

    

    
文件大小：
851K

    

    
代理商：
LC4064ZC-5M132C1


    

    

    

	
    
    
    

    
    
	
    Lattice Semiconductor
    ispMACH 4000V/B/C/Z Family Data Sheet
    13
    Figure 10. Global OE Generation for ispMACH 4032
    Zero Power/Low Power and Power Management
    The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and
    low power. With an advanced E
     low power cell and non sense-ampli
    fi
    er design approach (full CMOS logic
    approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low
    standby power without needing any “turbo bits” or other power management schemes associated with a traditional
    sense-ampli
    fi
    er approach. 
    2
    The zero power ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design
    changes, the ispMACH 4000Z family is able to achieve the industry’s “l(fā)owest static power”.
    IEEE 1149.1-Compliant Boundary Scan Testability
    All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows
    functional testing of the circuit board on which the device is mounted through a serial scan path that can access all
    critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
    test nodes, or test node data to be captured and shifted out for veri
    fi
    cation. In addition, these devices can be linked
    into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS
    interface that corresponds to the power supply voltage.
    I/O Quick Con
    fi
    guration
    To facilitate the most ef
    fi
    cient board test, the physical nature of the I/O cells must be set before running any continu-
    ity tests. As these tests are fast, by nature, the overhead and time that is required for con
    fi
    guration of the I/Os’
    physical nature should be minimal so that board test time is minimized. The ispMACH 4000 family of devices allows
    this by offering the user the ability to quickly con
    fi
    gure the physical nature of the I/O cells. This quick con
    fi
    guration
    takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's
    ispVM System programming software can either perform the quick con
    fi
    guration through the PC parallel port, or
    can generate the ATE or test vectors necessary for a third-party test system.
    Shared PTOE
    (Block 0)
    Shared PTOE
    (Block 1)
    Global
    Fuses
    GOE (3:0)
    to I/O cells
    Internal Global OE
    PT Bus
    (2 lines)
    4-Bit
    Global OE Bus
    Global OE
    Fuse connection
    Hard wired
    
    
    
    
    
    


    


    

    相關(guān)PDF資料
    		

    PDF描述
    		

    
    

    
LC4064ZC-5M56C
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs

    

    
LC4064ZC-5T100C
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs

    

    
LC4064ZC-5T48C
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs

    

    
LC4064ZC-75M132C1
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs

    

    
LC4384x
3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs

    

    

    

    


    


    

    相關(guān)代理商/技術(shù)參數(shù)
    		

    參數(shù)描述
    		

    
    

    
LC4064ZC-5M132I
功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
LC4064ZC-5M56C
功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
LC4064ZC-5M56I
功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
LC4064ZC-5MN132C
功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
LC4064ZC-5MN132I
功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100

    

    
    
    
    
	
    	
    
    
     
     
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