Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
32
ispMACH 4000V/B/C Timing Adders
1
Adder
Type
Base
Parameter
Description
-25
-27
-3
-35
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Optional Delay Adders
t
INDIO
t
INREG
Input register delay
Product term expander
delay
Output routing pool delay
Additional block loading
adder
—
0.95
—
1.00
—
1.00
—
1.00
ns
ns
t
EXP
t
MCELL
—
0.33
—
0.33
—
0.33
—
0.33
t
ORP
—
—
0.05
—
0.05
0.05
—
0.05
0.05
—
0.05
0.05
ns
ns
t
BLA
t
ROUTE
—
0.03
—
—
—
t
IOI
Input Adjusters
LVTTL_in
t
IN
, t
GCLK_IN
,
t
GOE
t
IN
, t
GCLK_IN
,
t
GOE
t
IN
, t
GCLK_IN
,
t
GOE
t
IN
, t
GCLK_IN
,
t
GOE
t
IN
, t
GCLK_IN
,
t
GOE
Using LVTTL standard
—
0.60
—
0.60
—
0.60
—
0.60
ns
LVCMOS33_in
Using LVCMOS 3.3
standard
Using LVCMOS 2.5
standard
Using LVCMOS 1.8
standard
Using PCI compatible
input
—
0.60
—
0.60
—
0.60
—
0.60
ns
LVCMOS25_in
—
0.60
—
0.60
—
0.60
—
0.60
ns
LVCMOS18_in
—
0.00
—
0.00
—
0.00
—
0.00
ns
PCI_in
—
0.60
—
0.60
—
0.60
—
0.60
ns
t
IOO
Output Adjusters
LVTTL_out
t
BUF
, t
EN
, t
DIS
Output con
fi
gured as
TTL buffer
Output con
fi
gured as
3.3V buffer
Output con
fi
gured as
2.5V buffer
Output con
fi
gured as
1.8V buffer
Output con
fi
gured as
PCI compatible buffer
Output con
fi
gured for
slow slew rate
—
0.20
—
0.20
—
0.20
—
0.20
ns
LVCMOS33_out t
BUF
, t
EN
, t
DIS
—
0.20
—
0.20
—
0.20
—
0.20
ns
LVCMOS25_out t
BUF
, t
EN
, t
DIS
—
0.10
—
0.10
—
0.10
—
0.10
ns
LVCMOS18_out t
BUF
, t
EN
, t
DIS
—
0.00
—
0.00
—
0.00
—
0.00
ns
PCI_out
t
BUF
, t
EN
, t
DIS
—
0.20
—
0.20
—
0.20
—
0.20
ns
Slow Slew
t
BUF
, t
EN
—
1.00
—
1.00
—
1.00
—
1.00
ns
Note: Open drain timing is the same as corresponding LVCMOS timing.
1. Refer to Technical Note TN1004:
ispMACH 4000 Timing Model Design and Usage Guidelines
for information regarding use of these adders.
