參數資料
型號： LC4032ZC-75T48C
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
中文描述： EE PLD, 7.5 ns, PQFP48
封裝： 1 MM HEIGHT, TQFP-48
文件頁數： 9/91頁
文件大?。?/td> 851K
代理商： LC4032ZC-75T48C
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
9
Output Routing Pool (ORP)
The Output Routing Pool allows macrocell outputs to be connected to any of several I/O cells within an I/O block.
This provides greater
fl
exibility in determining the pinout and allows design changes to occur without affecting the
pinout. The output routing pool also provides a parallel capability for routing macrocell-level OE product terms. This
allows the OE product term to follow the macrocell output as it is switched between I/O cells. Additionally, the out-
put routing pool allows the macrocell output or true and complement forms of the 5-PT bypass signal to bypass the
output routing multipliers and feed the I/O cell directly. The enhanced ORP of the ispMACH 4000 family consists of
the following elements:
Output Routing Multiplexers
OE Routing Multiplexers
Output Routing Pool Bypass Multiplexers
Figure 7 shows the structure of the ORP from the I/O cell perspective. This is referred to as an ORP slice. Each
ORP has as many ORP slices as there are I/O cells in the corresponding I/O block.
Figure 7. ORP Slice
Output Routing Multiplexers
The details of connections between the macrocells and the I/O cells vary across devices and within a device
dependent on the maximum number of I/Os available. Tables 5-9 provide the connection details.
Table 6. ORP Combinations for I/O Blocks with 8 I/Os
I/O Cell
Available Macrocells
I/O 0
M0, M1, M2, M3, M4, M5, M6, M7
I/O 1
M2, M3, M4, M5, M6, M7, M8, M9
I/O 2
M4, M5, M6, M7, M8, M9, M10, M11
I/O 3
M6, M7, M8, M9, M10, M11, M12, M13
I/O 4
M8, M9, M10, M11, M12, M13, M14, M15
I/O 5
M10, M11, M12, M13, M14, M15, M0, M1
I/O 6
M12, M13, M14, M15, M0, M1, M2, M3
I/O 7
M14, M15, M0, M1, M2, M3, M4, M5
Output Routing Multiplexer
OE Routing Multiplexer
ORP
Bypass
Multiplexer
From Macrocell
From PTOE
To I/O
Cell
To I/O
Cell
Output
OE
5-PT Fast Path
相關PDF資料
PDF描述
LC4064ZC-37T100C DIODE ZENER TRIPLE ISOLATED 200mW 27Vz 2mA-Izt 0.0704 0.1uA-Ir 18.9 SOT-363 3K/REEL
LC4064ZC-37M132C1 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
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相關代理商/技術參數
參數描述
LC4032ZC-75T48E 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4032ZC-75T48I 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4032ZC-75TN48C 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4032ZC-75TN48E 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
LC4032ZC-75TN48I 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAMMABLE SUPER FAST HI DENSITY PLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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