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參數(shù)資料
| 型號(hào)： | LC372100PM-20LV |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 2 MEG (262144 words x 8 bits) Mask ROM Internal Clocked Silicon Gate |
| 中文描述： | 2邁可（262144字× 8位）掩模ROM內(nèi)部時(shí)鐘硅門 |
| 文件頁(yè)數(shù)： | 5/5頁(yè) |
| 文件大?。?/td> | 79K |
| 代理商： | LC372100PM-20LV |
PS No. 5088-5/5
LC372100PP, PM, PT-10/20LV
This catalog provides information as of May, 1998. Specifications and information herein are subject to change
without notice.
I
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
I
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
I
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Timing Chart
System Design Notes
These LSIs adopt an internal synchronization technique in which operation is started by detecting changes in either the
CE input or the address inputs. As a result, the output data immediately after power on is invalid. Once power has been
applied, valid data is output after the application changes the value of either the CE input or at least one of the address
inputs.
Another point due to the use of the ATD technique is that these LSIs are extremely sensitive to input noise. Applications
must take precautions to provide stable input signals, both for the CE input and the address inputs, to prevent incorrect
operation.
相關(guān)PDF資料 |
PDF描述 |
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| LC372100PP-20LV | CAP 10UF 16V 20% TANT SMD-3528-21 TR-13 |
| LC372100PT-10LV | CAP 10UF 16V 10% TANT SMD-6032-28 TR-13 |
| LC372100PT-20LV | CAP 10UF 16V 10% TANT SMD-6032-28 TR |
| LC372100PP-10LV | 2 MEG (262144 words x 8 bits) Mask ROM Internal Clocked Silicon Gate |
| LC372100PM-10LV | 2 MEG (262144 words x 8 bits) Mask ROM Internal Clocked Silicon Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC372100PP | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:2 MEG (262144 words x 8 bits) Mask ROM Internal Clocked Silicon Gate |
| LC372100PP(LV) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC372100PP-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC372100PP-10LV | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:2 MEG (262144 words x 8 bits) Mask ROM Internal Clocked Silicon Gate |
| LC372100PP-20LV | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:2 MEG (262144 words x 8 bits) Mask ROM Internal Clocked Silicon Gate |
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