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參數(shù)資料
| 型號： | LC36256AML-12 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 256 K (32768 words x 8 bits) SRAM |
| 中文描述： | 256度（32768字× 8位）的SRAM |
| 文件頁數(shù)： | 6/7頁 |
| 文件大小： | 99K |
| 代理商： | LC36256AML-12 |
LC36256AL, AML-70/85/10/12
No. 4163-6/7
Write Cycle (2): CE Control
Note (6)
Notes
(1) t
COD
, t
OOD
, and t
WOD
are defined as the time at which the outputs becomes the high impedance state and
are not referred to output voltage levels.
(2) An external antiphase signal must not be applied when D
OUT
is in the output state.
(3) t
WP
is the time interval that CE and WE are low-level and is defined as the interval from the falling of WE
to the rising of CE or WE whichever is earlier.
(4) t
CW
is the time interval that CE and WE are low-level and is defined as the time from the falling of CE to
the rising of CE or WE whichever is earlier.
(5) D
OUT
goes to the high-impedance state when either OE is high-level, CE is high-level, or WE is low-level.
(6) When OE is high-level during the write cycle, D
OUT
goes to the high-impedance state.
Data Retention Characteristics
at Ta = 0 to +70°C
Parameter
Symbol
V
DR
Conditions
min
2.0
typ
*
max
5.5
10
2
1
Unit
Data retention supply voltage
V
CE
≥
V
CC
–0.2V
V
V
CC
= 3.0V,
V
CE
≥
2.8V
0 to +70°C
0 to +40°C
I
CCDR1
μA
Data retention supply current
25°C
0.25
I
CCDR2
V
CC
= 2.0 to 5.5V,
V
CE
≥
V
CC
–0.2V
0.5
25
μA
CE setup time
CE hold time
t
CDR
t
R
0
ns
ns
t
RC
**
* Reference values at V
CC
= 5V, Ta = 25°C ** t
RC
= Read Cycle time
Data Retention Waveform
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LC36256AML-12W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LC36256AML-70 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:256 K (32768 words x 8 bits) SRAM |
| LC36256AML-70W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LC36256AML-85 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:256 K (32768 words x 8 bits) SRAM |
| LC36256AML-85W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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