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參數(shù)資料
| 型號： | LC35256D |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 256K asynchronous silicon gate CMOS static RAM(256K異步硅門CMOS靜態(tài)RAM) |
| 中文描述： | 256K異步硅柵CMOS靜態(tài)RAM（256K異步硅門的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 107K |
| 代理商： | LC35256D |
No. 5823-7/8
LC35256D-10, LC35256DM, DT-70/10
Write Cycle 1 (WE write) *
6
Write Cycle 2 (CE write) *
6
Notes: 1. Applications must set WE high during the read cycle.
2. External circuits in the application must not apply reverse phase signals to the D
OUT
pins when those pins are in the output state.
3. The time t
WP
is the period when CE and WE are both low. It is defined as the time from the fall of WE to the rise of CE or the rise of WE, whichever
occurs first.
4. The time t
CW
is the period when CE and WE are both low. It is defined as the time from the fall of CE to the rise of CE or the rise of WE, whichever
occurs first.
5. The data outputs (D
OUT
) go to the high-impedance state if any one of the following conditions hold: OE is high, CE is high, or WE is low.
6. OE must be held either high or low during the write cycle.
7. The D
OUT
pins have the same phase as the write cycle write data.
*
5
*
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LC35256FT | 256K (32768 words X 8 bits) SRAM Control Pins: OE and CE |
| LC35256FT-55U | 256K (32768 words X 8 bits) SRAM Control Pins: OE and CE |
| LC35256FT-70U | 256K (32768 words X 8 bits) SRAM Control Pins: OE and CE |
| LC35256D-10 | Dual Control Pins: OE and CE 256K (32768-word X 8-bit) SRAM |
| LC35256DT-70 | Dual Control Pins: OE and CE 256K (32768-word X 8-bit) SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC35256D-10 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Dual Control Pins: OE and CE 256K (32768-word X 8-bit) SRAM |
| LC35256DM | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Dual Control Pins: OE and CE 256K (32768-word X 8-bit) SRAM |
| LC35256DM-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LC35256DM-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| LC35256DT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
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