
3. Current limiting circuit
The current limiting circuit performs limiting with the current determined from I = VRF/Rf (VRF = 0.5 Vtyp,
Rf: current detector resistance) (that is, this circuit limits the peak current).
Limiting operation includes decrease in the output on-duty to suppress the current.
4. Power save circuit
This IC enters the power save condition to decrease the current dissipation in the stop mode. In this condition, the bias
current of most of circuits is cut off. Even in the power save condition, the 5 V regulator output is given.
5. Reference clock
The reference clock for speed control can be entered in two ways as described below.
(1) Oscillation with a crystal oscillator
For oscillation with a crystal oscillator, connect X’tal and C, R as shown below.
This circuit and constant are for reference only. It is necessary that each manufacturer checks for problem because
of effects expected due to characteristics of a crystal oscillator and the floating capacity due to routing of a printed
circuit board.
(Cautions for routing of a printed circuit board)
The crystal oscillation circuit is a high-frequency circuit and readily influenced by the a printed circuit board
floating capacity, etc. Accordingly, due consideration must be made to shorten the wiring as much as possible for
external circuits and to reduce the wire width. In the external circuit, the wiring between the oscillator and C3 (C2)
is readily influenced particularly by the floating capacity, so that their routing requires particular attention. C4 is
highly effective in reducing the negative resistance at high frequency, but due attention is necessary not to reduce
excessively the negative resistance with the fundamental wave.
(2) External clock (a few MHz equivalent to the crystal oscillation frequency)
To enter the signal equivalent to the crystal oscillation frequency from the external signal source, enter the signal
via resistor (reference value: about 5.1 k
) in series with XI pin. In this case, the XO pin must be kept OPEN.
INPUT signal level
L level voltage 0 V to 0.8 V
H level voltage 2.5 V to 5.0 V
6. Speed lock range
The speed lock range is ±6.25% of the constant speed. If the motor speed falls inside the lock range, the LD pin goes
to “L” (open collector output). When the motor speed falls outside the lock range, the on-duty ratio of motor drive
output changes according to the speed error, causing control to keep the motor speed within the lock range.
C1, R1: For oscillation stabilization
C3: For oscillator connection
C2: For over-tone oscillation prevention and stabilization
C4: For over-tone oscillation prevention
No. 7099-9/12
LB1929
R1
C1
VREG
XI
XO
C2
C3
C4
Reference value
Oscillation frequency (MHz)
C1 (μF)
C2 (pF)
C3 (pF)
C4 (pF)
R1 (
)
330 k
3 to 5
0.1
15
47
10
5 to 8
0.1
10
47
None
330 k
8 to 10
0.1
10
22
None
330 k