參數(shù)資料
型號(hào)： LB11993W
元件分類(lèi)： 運(yùn)動(dòng)控制電子
英文描述： BRUSHLESS DC MOTOR CONTROLLER, PQFP64
封裝： 10 X 10 MM, SQFP-64
文件頁(yè)數(shù)： 9/15頁(yè)
文件大?。?/td> 162K
代理商： LB11993W
LB11993W
No.A0677-3/15
Continued from preceding page.
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
[FRC pin]
High-level voltage
VFRCH
2.5
VCC1
V
Low-level voltage
VFRCL
-0.2
0.4
V
Input current
IFRCIN
VFRC_C=3V
20
40
A
Leakage current
IFRCLK
VFRC_C=0V
-30
A
[VH]
Hall supply voltage
VHALL
IH=5mA, VH(+)-VH(-)
0.83
0.93
1.03
V
Minus (-) pin voltage
VH(-)
IH=5mA
0.90
0.97
1.04
V
[FG comparator]
Input offset voltage
VFGOFF
-3
+3
mV
Input bias current
IbFG
VFGIN+=VFGIN-=1.5V
500
nA
Input bias current offset
IbFG
VFGIN+=VFGIN-=1.5V
-100
100
nA
Common-mode input range
VFGCM
1.2
2.5
V
High-level output voltage
VFGOH
When internally pulled up
2.8
V
Low-level output voltage
VFGOL
When internally pulled up
0.2
V
Voltage gain
VGFG
Design target value, Note 1
100
dB
Output current (sink)
IFGOs
Output pin set to low
5
mA
Note 1: Design target value parameters are not tested.
Note 2: The standard for the overlap amount parameter is to report the measured value without change.
Cylinder Motor Driver Block at Ta=25
°C, VCC1=3V, VCC2=4.75V, VS=3V
Ratings
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply current 4
ICC2
IO=76mA, VSTBY_D=3V
VSTBY_C=0V
0.75
2.5
mA
Output quiescent current 4
ICC2Q
VSTBY_D=VSTBY_C=0V
100
A
Output quiescent current 5
IS(D)Q
VSTBY_D=VSTBY_C=0V
100
300
A
Output saturation voltage upper side 1
VOU1
IO=0.1A, RF=0.25
0.2
0.4
V
Output saturation voltage lower side 1
VOD1
IO=0.1A, RF=0.25
0.2
0.4
V
Output saturation voltage upper side 2
VOU2
IO=0.4A, VS=3V, RF=0.25
0.3
0.6
V
Output saturation voltage lower side 2
VOD2
IO=0.4A, VS=3V, RF=0.25
0.3
0.6
V
COM pin common-mode input voltage
range
VIC
0.3
VCC2-0.9
V
Standby pin high-level voltage
VSTBYH
2
VCC1V
Standby pin low-level voltage
VSTBYL
-0.2
0.7
V
Standby pin input current
ISTBYH
VSTBY_D=3V
50
A
Standby pin leakage current
ISTBYL
VSTBY_D=0V
-10
A
FRC pin high-level voltage
VFRCH
2
VCC1V
FRC pin low-level voltage
VFRCL
-0.2
0.7
V
FRC pin input current
IFRCI
VFRC_D=3V
50
A
FRC pin leakage current
IFRCL
VFRC_D=0V
-10
A
Slope pin source current ratio
RSOURCE
ICSLP1SOURCE/ICSLP2SOURCE
-20
20
%
Slope pin sink current ratio
RSINK
ICSLP1SINK/ICSLP2SINK
-20
20
%
CSLP1 source-to-sink current ratio
RCSLP1
ICSLP1SOURCE/ICSLP1SINK
-35
15
%
CSLP2 source-to-sink current ratio
RCSLP2
ICSLP2SOURCE/ICSLP2SINK
-35
15
%
Startup frequency
Freq
Cosc=0.1
F, OSC frequency
Design target value, Note 1
11.5
Hz
Phase delay width
Dwidth
Design target value, Note 1
30
deg
Note 1: Design target value parameters are not tested.
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