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參數(shù)資料
| 型號： | LB11985 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | VCR Capstan Motor Brushless Motor Driver |
| 中文描述： | 錄像機絞盤電機無刷電機驅動 |
| 文件頁數(shù)： | 2/9頁 |
| 文件大?。?/td> | 82K |
| 代理商： | LB11985 |
No. 6209-2/9
LB11985H
Electrical Characteristics
at Ta = 25°C, V
CC
= 5 V, V
S
= 15 V
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
V
CC
current drain
[Output]
I
CC
RL =
∞
, VCTL = 0 V (quiescent mode)
10
15
mA
Output saturation voltage
V
Osat
1
I
O
= 500 mA, Rf = 0.5
, Sink + Source
VCTL = VLIM = 5 V (with saturation prevention)
I
O
= 1.0 A, Rf = 0.5
, Sink + Source
VCTL = VLIM = 5 V (with saturation prevention)
2.2
2.7
V
V
Osat
2
2.8
3.7
V
Output leakage current
I
Oleak
1.0
mA
[FR]
FR pin input
Threshold voltage
V
FR
1
4
V
FR pin input
Input bias current
Ib (FR)
VFR = 5 V
100
150
μA
[BR]
BR pin input
Threshold voltage
V
BRTH
1
4
V
BR pin input
Input bias current
Ib (BR)
VBR = 5 V
100
150
μA
[Control]
CTLREF pin voltage
V
CREF
V
CREF
IN
Ib (CTL)
2.0
2.15
2.3
V
CTLREF pin input range
1
4
V
CTL pin input bias current
VCTL = 5 V, with CTLREF open
Rf = 0.5
, VLIM = 5 V, Io
≥
40 mA
With the Hall input logic states fixed (U, V, W = high, high, low)
Rf = 0.5
,
Io = 200 mA
With the Hall input logic states fixed (U, V, W = high, high, low)
5
μA
CTL pin control start voltage
V
CTL
(ST)
2.0
2.2
2.4
V
CTL pin control Gm
G
m
(CTL)
1.8
2.25
2.7
V
[Current Limiter]
LIM current limit offset voltage
V
off
(LIM)
Rf = 0.5
, VCTL = 5 V, Io
≥
40 mA
With the Hall input logic states fixed (U, V, W = high, high, low)
80
200
320
mV
LIM pin input bias current
Ib (LIM)
VCTL = 5 V,VREF: OPEN, VLIM = 0 V
Rf = 0.5
, VCTL = 5 V
With the Hall input logic states fixed (U, V, W = high, high, low)
–2
–1
μA
LIM pin current limit level
Gm (LIM)
0.37
0.47
0.57
mA
[Hall Amplifier]
Input offset voltage
V
off
(HALL)
I
b
(HALL)
V
cm
(HALL)
–6
+6
mV
Input bias current
1.0
3.0
μA
Common-mode input voltage
1.3
3.3
V
Torque ripple correction ratio
TRC
At the bottom and peak that occur in the Rf
waveform at 200 mA (Rf = 0.5
)
14.5
%
[FG Amplifier]
FG amplifier input offset voltage
V
off
(FG)
I
b
(FG)
V
Osat
(FG)
V
CM
(FG)
–8
+8
mV
FG amplifier input bias current
–100
nA
FG amplifier output saturation voltage
For the sink side, at the internal pull-up resistor
0.4
0.55
V
FG amplifier common-mode input voltage
1.0
4.0
V
[Saturation]
Saturation prevention circuit
lower side set voltage
V
Osat
(DET)
Io = 10 mA, Rf = 0.5
, VCTL = VLIM = 5 V
The voltages between the OUT-Rf pairs at full wave.
0.13
0.25
0.42
V
[Schmitt Amplifier]
Duty
DUTY
60 mVp-p, 1 kHz input
*
1
49
50
51
%
Upper side output saturation voltage
V
satu
(SH)
V
satd
(SH)
Vhys
4.8
V
Lower side output saturation voltage
0.2
V
Hysteresis
Design target values
*
2
45
mV
TSD operating temperature
T-TSD
T-TSD
Design target values
*
2
180
°C
TSD hysteresis
Design target values
*
2
15
°C
Note
*
1 : The ratings are just the measured value with no margin afforded.
*
2 : Items shown to be design target values in the conditions column are not measured.
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