參數(shù)資料
型號： LAN91C100FDREVD
廠商： SMSC Corporation
英文描述： FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述： 宴快速以太網(wǎng)控制器以全雙工能力
文件頁數(shù)： 35/79頁
文件大?。?/td> 585K
代理商： LAN91C100FDREVD
FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC DS – LAN91C100FD Rev. D
Page 35
Rev.
10/14/2002
PRELIMINARY
OFFSET
C
NAME
TYPE
WRITE ONLY
SYMBOL
ACK
INTERRUPT ACKNOWLEDGE
REGISTER
RX_DISC
INT
ERCV INT
RX_OVRN
INT
TX EMPTY
INT
TX INT
OFFSET
D
NAME
TYPE
SYMBOL
MSK
INTERRUPT MASK REGISTER
READ/WRITE
RX_DISC
INT
0
ERCV INT
EPH INT
RX_OVRN
INT
0
ALLOC
INT
0
TX EMPTY
INT
0
TX INT
RCV INT
0
0
0
0
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A
MASK bit being set will cause a hardware interrupt.
Note
:
The Bit 7 mask must never be written high (1).
RX_DISC INT - Set when the nRXDISC PIN COUNTER in the ERCV register increments to a value of FF.
The RX_DISC INT bit latches the condition for the purpose of being polled or generating an interrupt, and
will only be cleared by writing the acknowledge register with the RX_DISC INT bit set.
ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of
bytes received into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch).
ERCV INT stays set until acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the
ERCV INT bit set.
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible special
conditions. This bit merges exception type of interrupt sources, whose service time is not critical to the
execution speed of the low level drivers. The exact nature of the interrupt can be obtained from the EPH
Status Register (EPHSR), and enabling of these sources can be done via the Control Register. The
possible sources are:
1. LINK - Link Test transition
2. CTR_ROL - Statistics counter roll over
3. TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low
and the specific reason will be reflected by the bits:
3.1
TXUNRN - Transmit under-run
3.2
SQET - SQE Error
3.3
LOST CARR - Lost Carrier
3.4
LATCOL - Late Collision
3.5
16COL - 16 collisions
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control Register.
1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit Error
Enable)
EPH INT will only be cleared by the following methods:
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LAN91C100-FD-SS 制造商:SMSC 制造商全稱:SMSC 功能描述:FEAST Fast Ethernet Controller with Full Duplex Capability
LAN91C100FD-SS 功能描述:以太網(wǎng) IC Non-PCI 10/100 Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
LAN91C100-FD-ST 制造商:SMSC 制造商全稱:SMSC 功能描述:FEAST Fast Ethernet Controller with Full Duplex Capability
LAN91C100FD-ST 功能描述:以太網(wǎng) IC Non-PCI 10/100 Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
LAN91C100FDTQFP 功能描述:以太網(wǎng) IC Non-PCI 10/100 Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray
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