參數(shù)資料
型號: LAN91C100FDREVB
廠商: SMSC Corporation
英文描述: FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述: 宴快速以太網(wǎng)控制器以全雙工能力
文件頁數(shù): 57/79頁
文件大?。?/td> 585K
代理商: LAN91C100FDREVB
FEAST Fast Ethernet Controller with Full Duplex Capability
SMSC DS – LAN91C100FD Rev. D
Page 57
Rev.
10/14/2002
PRELIMINARY
VL BUS
SIGNAL
nBE0 nBE1
nBE2 nBE3
nADS
LAN91C100
SIGNAL
nBE0 nBE1
nBE2 nBE3
nADS, nCYCLE
NOTES
Byte enables. Latched transparently by nADS rising edge.
Address Strobe is connected directly to the VL bus. nCYCLE is
created typically by using nADS delayed by one LCLK.
Typically uses the interrupt lines on the ISA edge connector of
VL bus
32 bit data bus. The bus byte(s) used to access the device are a
function of nBE0-nBE3:
nBE0
nBE1
nBE2
nBE3
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
Not used = tri-state on reads, ignored on writes. Note that nBE2
and nBE3 override the value of A1, which is tied low in this
application.
nLDEV is a totem pole output. nLDEV is active on valid decodes
of A15-A4 and AEN=0.
UNUSED PINS
IRQn
INTR0-INTR3
D0-D31
D0-D31
Double word access
Low word access
High word access
Byte 0 access
Byte 1 access
Byte 2 access
Byte 3 access
nLDEV
nLDEV
VCC
GND
OPEN
nRD nWR
A1 nVLBUS
nDATACS
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