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參數(shù)資料
| 型號： | LAN8700-AEZG |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, QCC36 |
| 封裝： | 6 X 6 MM, 0.90 MM HEIGHT, GREEN, QFN-36 |
| 文件頁數(shù)： | 15/73頁 |
| 文件大小： | 457K |
| 代理商： | LAN8700-AEZG |
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±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR
TM
in a Small Footprint
Datasheet
SMSC LAN8700/LAN8700I
15
Revision 1.0 (02-09-07)
DATASHEET
Table 3.3 Management Signals
SIGNAL NAME
TYPE
DESCRIPTION
MDIO
I/O
Management Data Input/OUTPUT
: Serial management data
input/output.
MDC
I
Management Clock
:
Serial management clock.
Table 3.4 Boot Strap Configuration Inputs (
Note 3.1
)
SIGNAL NAME
TYPE
DESCRIPTION
CRS/
PHYAD4
I/O
PHY Address Bit 4:
set the
default address of the PHY. This
signal is mux’d with CRS
Note:
This signal is mux’d with CRS
FDUPLEX/
PHYAD3
I/O
PHY Address Bit 3:
set the
default address of the PHY.
Note:
This signal is mux’d with FDUPLEX
ACTIVITY/
PHYAD2
I/O
PHY Address Bit 2:
set the
default address of the PHY.
Note:
This signal is mux’d with ACTIVITY
LINK/
PHYAD1
I/O
PHY Address Bit 1:
set the
default address of the PHY.
Note:
This signal is mux’d with LINK
SPEED100/
PHYAD0
I/O
PHY Address Bit 0:
set the
default address of the PHY.
Note:
This signal is mux’d with SPEED100
RXD2/
MODE2
I/O
PHY Operating Mode Bit 2:
set the default MODE of the PHY.
See
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 52
, for
the MODE options.
Note:
This signal is mux’d with RXD2
RXD1/
MODE1
I/O
PHY Operating Mode Bit 1:
set the default MODE of the PHY.
See
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 52
, for
the MODE options.
Note:
This signal is mux’d with RXD1
RXD0/
MODE0
I/O
PHY Operating Mode Bit 0:
set the default MODE of the PHY.
See
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 52
, for
the MODE options.
Note:
This signal is mux’d with RXD0
RX_CLK/
REGOFF
I/O
Internal Regulator off:
disable the internal +1.8v regulator.
This signal is mux’d with RX_CLK.
Float to enable the internal +1.8v regulator.
Pull up with a resistor (see
Table 4.3, “Boot Strapping
Configuration Resistors,” on page 32
) to VDDIO to disable the
internal regulator.
COL/
RMII/
CRS_DV
I/O
Digital Communication Mode:
set the digital communications
mode of the PHY to RMII or MII. This signal is muxed with the
Collision signal (MII mode) and Carrier Sense/ receive Data Valid
(RMII mode)
Float for MII mode.
Pull up with a resistor to VDDIO for RMII mode (see
Table 4.3,
“Boot Strapping Configuration Resistors,” on page 32
) .
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