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參數(shù)資料
| 型號(hào)： | LAN83C185-JD |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, TQFP-64 |
| 文件頁數(shù)： | 20/22頁 |
| 文件大?。?/td> | 166K |
| 代理商： | LAN83C185-JD |
SMSC DS – LAN83C180
Page 20
Rev. 08/24/2001
EXTERNAL COMPONENTS
Connecting an External 25MHz Reference
If an external clock is used then it should be driven into the REFCLK input, and XTAL1 must be connected to
OSCVDD. XTAL2 must be left unconnected.
nRESET Pull-up Resistor
This resistor is required regardless of whether nRESET is used externally.
RX Input Decoupling
The method of using a split input load resistor and de-coupling the center tap reduces common mode noise.
Crystal Oscillator
For IEEE802.3 compliance the oscillator must run at 25MHz ±100ppm. The LAN83C180 on-chip circuitry contributes
less than 40ppm variability to the oscillator frequency, therefore the crystal must be specified to 60ppm. This must
include variations due to temperature and aging.
External capacitors are required on the XTAL1 & XTAL2 pins. The values of these capacitors are dependent on the
power dissipation and the equivalent series resistance of the chosen crystal, as follows:
Let
P
C
= power dissipation of the crystal in mW,
and
ESR
= equivalent series resistance of the crystal in W.
If
P
C
>2.6mW then
C
1
&
C
2
are determined by the loop gain:
If
P
C
<2.6mW then
C
1
&
C
2
are determined by the power dissipation of the crystal:
Tracking to the crystal and the capacitors must be as short as possible. Other signal paths must not cross the area.
The LAN83C180 is supported by magnetics from the following vendors:
VENDOR
Bel
Pulse
Valor
HALO
HALO
MAGNETICS
S558-5999-39
H1012
ST6118
TG110-S050N2
TG22-3506ND
C1
C2=
=
184
ESR
-7pF
C1
C2=
=
114
Pc
ESR
-7pF
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