參數(shù)資料
型號(hào)： LAN83C183
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 網(wǎng)絡(luò)接口
英文描述： FAST ETHERNET PHYSICAL LAYER DEVICE
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝： TQFP-64
文件頁(yè)數(shù)： 11/22頁(yè)
文件大?。?/td> 166K
代理商： LAN83C183
SMSC DS – LAN83C180
Page 11
Rev. 08/24/2001
A false CRS event happens if, at the beginning of a carrier event, the JK symbols are not received correctly.
When the LAN83C180 is in 100M mode it will count all false CRS events in register 27 bits 7:0. This counter is self
cleared upon read. If a disconnect event occurs between the consecutive reads of register 27, bit 15 in the register
will set high.
ICFG - Interrupt
The LAN83C183 offers an "MII" interrupt output which can be used to interrupt the host whenever a change in link
status occurs - this output is multiplexed onto either the ACTST or COLST pins. When ICFG is high MINT (the MII
interrupt) replaces COLST on pin 8. With ICFG low MINT is output on ACTST (pin 7) and activity is now indicated on
the LINKST pin 15 as follows:
No Link - LINKST High
Link, no Activity - LINKST Low
Link, Activity - LINKST Toggles (for flashing LED)
MINT is active low by default, but may be inverted by writing bit 12 of register 24.
MINT will be asserted whenever a change in link status occurs (loss of link/gaining link). MINT will remain asserted
until the controller acknowledges the interrupt by writing to register 21 (any data pattern will accepted).
Should one or more link status change occur between the assertion of MINT and an acknowledge then a further
interrupt will be deasserted and then reasserted (min deassertion time 100ns, max 150ns).
Only a single interrupt event may be queued at any one time. Multiple status changes between acknowledge events
will generate only a single queued interrupt.
Auto-Negotiation Enable (ANEN)
Auto-negotiation may be disabled on reset by setting the ANEN pin to logic zero. During operation, auto-negotiation
can be disabled by setting the ANEN pin low or by setting bit 12 of register 0 to zero. If auto-negotiate is disabled,
the LAN83C180 will lose the link, and link will be re-established only after the LAN83C180 control state machine has
determined the speed.
MII Management Interface
The management interface is a 2 wire serial interface connecting a PHY to a management entity. The management
unit controls the PHY and gathers information on the status of the PHY. It does this via the implemented registers.
相關(guān)PDF資料
PDF描述
LAN83C185-JD HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER
LAN83C185-JT HIGH PERFORMANCE SINGLE CHIP LOW POWER 10/100 ETHERNET PHYSICAL LAYER TRANSCEIVER
LAN8700 【15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR TM in a Small Footprint
LAN9115 HIGHLY EFFICIENT SINGLE - CHIP 10/100 NON PCI ETHERNET CONTROLLER
LAN9115-MD HIGHLY EFFICIENT SINGLE - CHIP 10/100 NON PCI ETHERNET CONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LAN83C183-JD 制造商:SMSC 制造商全稱:SMSC 功能描述:FAST ETHERNET PHYSICAL LAYER DEVICE
LAN83C185 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver
LAN83C185_03 制造商:SMSC 制造商全稱:SMSC 功能描述:High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver
LAN83C185-JD 功能描述:電信線路管理 IC Lo Pwr 10/100 3.3V PHY RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
LAN83C185JT 制造商:SMSC 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*