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參數(shù)資料
| 型號： | LAMXO2280E-3TN144E |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 40/77頁 |
| 文件大小： | 0K |
| 描述： | IC FPGA AUTO 2.28KLUTS 144-TQFP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | LA-MachXO |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 5.1ns |
| 電壓電源 - 內(nèi)部： | 1.14 V ~ 1.26 V |
| 宏單元數(shù)： | 1140 |
| 輸入/輸出數(shù)： | 113 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
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November 2007
Data Sheet DS1003
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
www.latticesemi.com
4-1
DS1003 Pinouts_01.3
Signal Descriptions
Signal Name
I/O
Descriptions
General Purpose
P[Edge] [Row/Column
Number]_[A/B/C/D/E/F]
I/O
[Edge] indicates the edge of the device on which the pad is located. Valid edge designa-
tions are L (Left), B (Bottom), R (Right), T (Top).
[Row/Column Number] indicates the PFU row or the column of the device on which the
PIO Group exists. When Edge is T (Top) or (Bottom), only need to specify Row Number.
When Edge is L (Left) or R (Right), only need to specify Column Number.
[A/B/C/D/E/F] indicates the PIO within the group to which the pad is connected.
Some of these user programmable pins are shared with special function pins. When not
used as special function pins, these pins can be programmed as I/Os for user logic.
During conguration of the user-programmable I/Os, the user has an option to tri-state the
I/Os and enable an internal pull-up resistor. This option also applies to unused pins (or
those not bonded to a package pin). The default during conguration is for user-program-
mable I/Os to be tri-stated with an internal pull-up resistor enabled.
GSRN
I
Global RESET signal (active low). Dedicated pad, when not in use it can be used as an I/O
pin.
TSALL
I
TSALL is a dedicated pad for the global output enable signal. When TSALL is high all the
outputs are tristated. It is a dual function pin. When not in use, it can be used as an I/O pin.
NC
—
No connect.
GND
—
GND - Ground. Dedicated pins.
VCC
—
VCC - The power supply pins for core logic. Dedicated pins.
VCCAUX
—
VCCAUX - the Auxiliary power supply pin. This pin powers up a variety of internal circuits
including all the differential and referenced input buffers. Dedicated pins.
VCCIOx
—VCCIO - The power supply pins for I/O Bank x. Dedicated pins.
SLEEPN
1
I
Sleep Mode pin - Active low sleep pin. When this pin is held high, the device operates nor-
mally. This pin has a weak internal pull-up, but when unused, an external pull-up to VCC is
recommended. When driven low, the device moves into Sleep mode after a specied time.
PLL and Clock Functions (Used as user programmable I/O pins when not used for PLL or clock pins)
[LOC][0]_PLL[T, C]_IN
—
Reference clock (PLL) input Pads: [LOC] indicates location. Valid designations are ULM
(Upper PLL) and LLM (Lower PLL). T = true and C = complement.
[LOC][0]_PLL[T, C]_FB
—
Optional feedback (PLL) input Pads: [LOC] indicates location. Valid designations are ULM
(Upper PLL) and LLM (Lower PLL). T = true and C = complement.
PCLK [n]_[1:0]
—
Primary Clock Pads, n per side.
Test and Programming (Dedicated pins)
TMS
I
Test Mode Select input pin, used to control the 1149.1 state machine.
TCK
I
Test Clock input pin, used to clock the 1149.1 state machine.
TDI
I
Test Data input pin, used to load data into the device using an 1149.1 state machine.
TDO
O
Output pin -Test Data output pin used to shift data out of the device using 1149.1.
1. Applies to LA-MachXO “C” devices only. NC for “E” devices.
LA-MachXO Automotive Family Data Sheet
Pinout Information
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