參數(shù)資料
型號： LAMXO2280E-3FTN324E
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 9/77頁
文件大?。?/td> 0K
描述： IC FPGA AUTO 2.28KLUTS 324-BGA
標(biāo)準(zhǔn)包裝： 84
系列： LA-MachXO
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 5.1ns
電壓電源 - 內(nèi)部： 1.14 V ~ 1.26 V
宏單元數(shù)： 1140
輸入/輸出數(shù)： 271
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 324-LBGA
供應(yīng)商設(shè)備封裝： 324-FTBGA（19x19）
包裝： 托盤
2-14
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
PIO Groups
On the LA-MachXO devices, PIO cells are assembled into two different types of PIO groups, those with four PIO
cells and those with six PIO cells. PIO groups with four IOs are placed on the left and right sides of the device while
PIO groups with six IOs are placed on the top and bottom. The individual PIO cells are connected to their respec-
tive sysIO buffers and PADs.
On all LA-MachXO devices, two adjacent PIOs can be joined to provide a complementary Output driver pair. The I/
O pin pairs are labeled as "T" and "C" to distinguish between the true and complement pins.
The LA-MachXO1200 and LA-MachXO2280 devices contain enhanced I/O capability. All PIO pairs on these larger
devices can implement differential receivers. In addition, half of the PIO pairs on the left and right sides of these
devices can be congured as LVDS transmit/receive pairs. PIOs on the top of these larger devices also provide PCI
support.
Figure 2-15. Group of Four Programmable I/O Cells
Figure 2-16. Group of Six Programmable I/O Cells
PIO
The PIO blocks provide the interface between the sysIO buffers and the internal PFU array blocks. These blocks
receive output data from the PFU array and a fast output data signal from adjacent PFUs. The output data and fast
PIO B
PIO C
PIO D
PIO A
PADA "T"
PADB "C"
PADC "T"
PADD "C"
Four PIOs
This structure is used on the
left and right of MachXO devices
PIO B
PIO C
PIO D
PIO A
PADA "T"
PADB "C"
PADC "T"
PADD "C"
Six PIOs
PIO E
PIO F
PADE "T"
PADF "C"
This structure is used on the top
and bottom of MachXO devices
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