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參數(shù)資料
| 型號： | LA9705W |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | SQFP-64 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 177K |
| 代理商： | LA9705W |
No. 7771-3/15
LA9705W
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
TEGAIN1
TEG1
Input to pins A10 and A11, pin 25 = 0 V,
10.7
15.2
19.7
dB
pin 32 = SREF – 0.75 V, pin 36 = SREF. pin 40
TEGAIN2
TEG2
Input to pins A10 and A11, pin 25 = 0 V,
32.6
35.6
38.5
dB
pin 32 = SREF + 0.75 V, pin 36 = SREF, pin 40
TEGAIN3
TEG3
Input to pins A10 and A11, pin 25 = 5 V,
24.3
29.8
35.3
dB
pin 32 = SREF – 0.75 V, pin 36 = SREF, pin 40
TEOST
TOST
Pins A10 and A11 = PREF, pin 25 = 0 V,
SREF – 0.3
SREF
SREF + 0.3
V
pin 32 = SREF, pin 36 = SREF, pin 40
Input to pins A10 and A11, pin 25 = 0 V,
TEBAL1
TBAL1
pin 32 = SREF, pin 36 = SREF – 0.75 V
5.3
8.3
11.3
dB
The D gain at pin 40
Input to pins A10 and A11, pin 25 = 0 V,
TEBAL2
TBAL2
pin 32 = SREF, pin 36 = SREF + 0.75 V
–11.3
–8.3
–5.3
dB
The D gain at pin 40
With RL = 6.8 K
, the voltage difference at pin 39 between:
DPD phase difference
(1) Inputs of 5 MHz with a phase of 0° to pins A1, A3, A4,
Voltage difference 1
PD1
and A5 and 5 MHz with a phase of 36° to pin A2, and
0.39
0.51
0.66
V
(2) Inputs of 5 MHz with a phase of 0° to pins A1, A3, A4,
and A5 and 5 MHz with a phase of –36° to pin A2.
With RL = 6.8 K
, the voltage difference at pin 39 between:
DPD phase difference
(1) Inputs of 5 MHz with a phase of 0° to pins A1, A2, A4,
Voltage difference 2
PD2
and A5 and 5 MHz with a phase of 36° to pin A3, and
–0.66
–0.51
–0.39
V
(2) Inputs of 5 MHz with a phase of 0° to pins A1, A2, A4,
and A5 and 5 MHz with a phase of –36° to pin A3.
With RL = 6.8 K
, the voltage difference at pin 39 between:
DPD phase difference
(1) Inputs of 5 MHz with a phase of 0° to pins A1, A2, A3,
Voltage difference 3
PD3
and A5 and 5 MHz with a phase of 36° to pin A4, and
0.39
0.51
0.66
V
(2) Inputs of 5 MHz with a phase of 0° to pins A1, A2, A3,
and A5 and 5 MHz with a phase of –36° to pin A4.
With RL = 6.8 K
, the voltage difference at pin 39 between:
DPD phase difference
(1) Inputs of 5 MHz with a phase of 0° to pins A1, A2, A3,
Voltage difference 4
PD4
and A4 and 5 MHz with a phase of 36° to pin A5, and
–0.66
–0.51
–0.39
V
(2) Inputs of 5 MHz with a phase of 0° to pins A1, A2, A3,
and A4 and 5 MHz with a phase of –36° to pin A5.
DPD offset
DPDOF
With a 5 MHz signal applied to pins A1, A2, A3, A4,
SREF – 0.3
SREF
SREF + 0.3
V
and A5. RL = 6.8 K
APC1 reference voltage
LDS1
Pin 21 = 5 V, pin 15
150
180
200
mV
APC1 off
LDD1
Pin 21 = 0 V, pin 15
4.5
5
V
APC2 reference voltage
LDS2
Pin 22 = 5 V, pin 17
150
180
200
mV
APC2 off
LDD2
Pin 22 = 0 V, pin 17
4.5
5
V
With a 700 mVp-p signal input to pin 61
RFTHD
Pins 23, 25, and 26 at 0 V.
12
%
Pin 33 = SREF + 0.35 V, pin 34 = SREF – 0.14 V
Pin 59 = SREF. Pins 54 and 55.
Continued from preceding page.
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